NRF52840 PMU details

RE: NRF52840 PMU details

Mickael — Thu, 01 Mar 2018 08:39:28 GMT

thats clear - thanks again Hakon.

RE: NRF52840 PMU details

haakonsh — Thu, 01 Mar 2018 08:29:39 GMT

DCDC will operate in 'refresh' modes when in a low power state. The regulator will wake up periodically to top off the supply.

RE: NRF52840 PMU details

Mickael — Wed, 28 Feb 2018 17:55:49 GMT

Hi Haakonsh,

one additionnal question on this front:

is DCDC1 ON/OFF only controlled by the register setting? Or does the PMU decide to revert back to LDO when in very low power state? For example, in SYSTEM OFF is DCDC1 still enabled?

Mickael

RE: NRF52840 PMU details

haakonsh — Thu, 01 Feb 2018 13:03:59 GMT

Hey Mickael,

The 'PMU' is a complete black box with the following settings; DCDC0 ON/OFF + output voltage, DCDC1 ON/OFF, System ON, System OFF, and RAM retention.
This black box monitors the status of the CPU and each peripheral and adjust the regulators for optimal performance for any given system state.

When the ARM CPU is put to sleep(System ON) with the WFE instruction the MPU will automagically adjust the regulators. This is also true when the CPU is woken up, a peripheral is enabled/disabled, or when you enter/exit deep sleep(System OFF).

Cheers,

Håkon.