nRF51822, max IO pin voltage while off?

RE: nRF51822, max IO pin voltage while off?

Ole Morten — Tue, 20 Aug 2013 06:37:28 GMT

Yes, powering the chip through a GPIO will most likely be possible on the nRF51822, so this should be avoided.

If you found my answer useful however, I'd be happy if you could click the "Accept as answer" button below it, to mark this question as resolved. :-)

RE: nRF51822, max IO pin voltage while off?

Frank Zhao — Mon, 19 Aug 2013 14:08:36 GMT

Thanks for the answer

From what I've seen with other brands and architectures, leaking power into a pin while the power is off could potentially cause the current to leak into VDD via internal clamping diodes on the pin (or ESD protection diodes). Some low power CPU can actually start executing code if no brownout protection is implemented.

I have edited my design to use a open drain design instead

RE: nRF51822, max IO pin voltage while off?

Ole Morten — Mon, 19 Aug 2013 07:59:48 GMT

As you can see in table 13 of the PS, doing this would violate the specification, since the I/O pin voltage would be above VDD+0.3 V (VDD being 0 in your case, but the I/O being 3 V). The exact effect of this is unknown, but this is not something I'd recommend you to test.

Depending on your application, I would consider to leave the nRF51822 continously powered, but just set it in system off when not needed, not actually turn it off. If you do, and have VDD > 2.7 V, you are also allowed to have 3 V on a pin all the time. The chip is supposed to consume < 1 µA in this mode, but due to a PAN, current revisions might consume more. This will be fixed in the upcoming revision.