https://devzone.nordicsemi.com/f/nordic-q-a/3224/clarification-on-swdclk-requirementsAccording to the nRF51 series reference manual. 10.1.2 Debug interface mode Debug interface mode is initiated by clocking one clock cycle on SWDCLK with SWDIO=1. Due to delays caused by starting up the DAP's power domain, a minimum of 150 clocken-USTelligent Community 13Tue, 14 Nov 2017 10:43:53 GMT