nrf51822-ceaa package PCB questions

RE: nrf51822-ceaa package PCB questions

Jamie — Tue, 27 Aug 2013 15:07:16 GMT

BTW, a few follow-up questions (any that you can answer would be most helpful):

Can you perhaps suggest a few suitable examples of an epoxy or resin to coat the CEAA package with?

What is the expected mean-time-to-failure for a chip that is not appropriately protected?

What are expected symptoms of a chip that has been compromised through light exposure?

Precisely how should one coat the chip with appropriate epoxies/resins? Which location of the package needs protection, and to what depth of epoxy coverage is needed?

Thanks! Jamie

RE: nrf51822-ceaa package PCB questions

Jamie — Tue, 27 Aug 2013 15:01:39 GMT

Thanks, Ole!

RE: nrf51822-ceaa package PCB questions

Ole Morten — Tue, 27 Aug 2013 07:13:08 GMT

Sorry for the delay in answering. You're right that the problem with solder flowing down the via is avoided by filling the vias before soldering.

The CSP package is most definitely production-ready, and from a pure technical perspective there isn't any particular reason to not use it, except for the light-sensitivity as you say. This can for example be avoided by putting epoxy or similar over it.

In addition, you will often need a 4-layer PCB with finer resolution to be able to fully use all I/Os, so it might increase the cost of the hardware design. The CSP chip itself may also be more expensive than the QFN variant, but this is something you should check with your distributor.

RE: nrf51822-ceaa package PCB questions

Jamie — Mon, 26 Aug 2013 17:38:27 GMT

I resolved my own question about the vias-in-pads: seems the fab house can fill the vias with copper and then planarize them; not sure if all fab houses can do this.

Still need a response to my question about the production readiness of the CEAA chip-scale package, though.

Thanks! Jamie