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<?xml-stylesheet type="text/xsl" href="https://devzone.nordicsemi.com/cfs-file/__key/system/syndication/rss.xsl" media="screen"?><rss version="2.0" xmlns:dc="http://purl.org/dc/elements/1.1/" xmlns:slash="http://purl.org/rss/1.0/modules/slash/" xmlns:wfw="http://wellformedweb.org/CommentAPI/" xmlns:atom="http://www.w3.org/2005/Atom"><channel><title>Can WDT reset be postponed?</title><link>https://devzone.nordicsemi.com/f/nordic-q-a/33261/can-wdt-reset-be-postponed</link><description>I am working with the nRF52832, SDK14.0.0. I want to perform a flash write on a watchdog reset to save the current state. However, the watchdog resets after two cycles of the 32 MHz clock, which is not enough time to finish the data processing I want</description><dc:language>en-US</dc:language><generator>Telligent Community 13</generator><lastBuildDate>Mon, 23 Apr 2018 21:57:58 GMT</lastBuildDate><atom:link rel="self" type="application/rss+xml" href="https://devzone.nordicsemi.com/f/nordic-q-a/33261/can-wdt-reset-be-postponed" /><item><title>RE: Can WDT reset be postponed?</title><link>https://devzone.nordicsemi.com/thread/129418?ContentTypeID=1</link><pubDate>Mon, 23 Apr 2018 21:57:58 GMT</pubDate><guid isPermaLink="false">137ad170-7792-4731-bb38-c0d22fbe4515:51802bb7-de5f-470f-b4a3-7ae5e3a3003b</guid><dc:creator>flopash</dc:creator><description>&lt;p&gt;I wanted to follow up with this. I looked into the documentation and for the nRF52832, the time to write one 32-bit word appears to be a minimum of 67.5 us (&lt;a href="https://infocenter.nordicsemi.com/index.jsp?topic=%2Fcom.nordic.infocenter.sdk5.v14.0.0%2Fmigration.html"&gt;https://infocenter.nordicsemi.com/index.jsp?topic=%2Fcom.nordic.infocenter.sdk5.v14.0.0%2Fmigration.html&lt;/a&gt;).&lt;/p&gt;
&lt;p&gt;This would not have enough time to complete the write before the watchdog reset. Is this accurate, or am I missing something else?&amp;nbsp;&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item><item><title>RE: Can WDT reset be postponed?</title><link>https://devzone.nordicsemi.com/thread/127706?ContentTypeID=1</link><pubDate>Wed, 11 Apr 2018 02:02:40 GMT</pubDate><guid isPermaLink="false">137ad170-7792-4731-bb38-c0d22fbe4515:140c944c-d8e5-4610-bc1f-61f9a7c878e5</guid><dc:creator>Susheel Nuguru</dc:creator><description>&lt;p&gt;Two things&lt;/p&gt;
&lt;p&gt;&lt;/p&gt;
&lt;p&gt;1)&amp;nbsp; Giving any&amp;nbsp;ability to postpone reset (more than what is allowed) after WDT timeout will fail the purpose of the watchdog.&amp;nbsp;&lt;/p&gt;
&lt;p&gt;2) It is not two cycles of 32MHz but two clock cycles of 32KHz&lt;/p&gt;
&lt;h2 class="title topictitle2" id="ariaid-title4"&gt;Watchdog reset&lt;/h2&gt;
&lt;div class="body conbody"&gt;
&lt;p class="shortdesc"&gt;A TIMEOUT event will automatically lead to a watchdog reset.&lt;/p&gt;
&lt;p class="p"&gt;See&lt;span&gt;&amp;nbsp;&lt;/span&gt;&lt;a class="xref" title="Several sources may trigger a reset." href="http://infocenter.nordicsemi.com/topic/com.nordic.infocenter.nrf52840.ps/power.html#unique_747356178"&gt;Reset&lt;/a&gt;&lt;span&gt;&amp;nbsp;&lt;/span&gt;for more information about reset sources. If the watchdog is configured to generate an interrupt on the TIMEOUT event, the watchdog reset will be postponed with two 32.768 kHz clock cycles after the TIMEOUT event has been generated. Once the TIMEOUT event has been generated, the impending watchdog reset will always be effectuated.&lt;/p&gt;
&lt;p class="p"&gt;That should give you enough time to write one word to flash as it takes about 40uS to do so.&lt;/p&gt;
&lt;table class="table parameter" id="unique_432169175__flash_programming" border="1" cellpadding="4" cellspacing="0" frame="border" rules="all" summary=""&gt;
&lt;tbody class="tbody"&gt;
&lt;tr class="row param" id="unique_432169175__t_write"&gt;
&lt;td class="entry nocellnorowborder" colspan="1" headers="d693994e7789" rowspan="1"&gt;t&lt;sub class="ph sub"&gt;WRITE&lt;/sub&gt;&lt;/td&gt;
&lt;td class="entry nocellnorowborder" colspan="1" headers="d693994e7792" rowspan="1"&gt;
&lt;p class="p"&gt;Time to write one 32-bit word&lt;/p&gt;
&lt;/td&gt;
&lt;td class="entry nocellnorowborder" colspan="1" headers="d693994e7795" rowspan="1"&gt;&lt;/td&gt;
&lt;td class="entry nocellnorowborder" colspan="1" headers="d693994e7798" rowspan="1"&gt;&lt;/td&gt;
&lt;td class="entry nocellnorowborder" colspan="1" headers="d693994e7801" rowspan="1"&gt;&lt;/td&gt;
&lt;td class="entry nocellnorowborder" colspan="1" headers="d693994e7805" rowspan="1"&gt;&lt;span class="ph" id="unique_432169175__t_write.min"&gt;&lt;/span&gt;&lt;/td&gt;
&lt;td class="entry nocellnorowborder" colspan="1" headers="d693994e7808" rowspan="1"&gt;&lt;span class="ph" id="unique_432169175__t_write.typ"&gt;&lt;/span&gt;&lt;/td&gt;
&lt;td class="entry nocellnorowborder" colspan="1" headers="d693994e7811" rowspan="1"&gt;&lt;span class="ph" id="unique_432169175__t_write.max"&gt;41&lt;a class="xref" href="http://infocenter.nordicsemi.com/topic/com.nordic.infocenter.nrf52840.ps/nvmc.html?cp=2_0_0_3_2_9#unique_432169175__nvmc_el_spec_fn"&gt;&lt;sup&gt;1&lt;/sup&gt;&lt;/a&gt;&lt;/span&gt;&lt;/td&gt;
&lt;td class="entry nocellnorowborder" colspan="1" headers="d693994e7814" rowspan="1"&gt;&amp;micro;s&lt;/td&gt;
&lt;/tr&gt;
&lt;/tbody&gt;
&lt;/table&gt;
&lt;/div&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item></channel></rss>