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<?xml-stylesheet type="text/xsl" href="https://devzone.nordicsemi.com/cfs-file/__key/system/syndication/rss.xsl" media="screen"?><rss version="2.0" xmlns:dc="http://purl.org/dc/elements/1.1/" xmlns:slash="http://purl.org/rss/1.0/modules/slash/" xmlns:wfw="http://wellformedweb.org/CommentAPI/" xmlns:atom="http://www.w3.org/2005/Atom"><channel><title>LF &amp;amp; HF clock configuration with softdevice</title><link>https://devzone.nordicsemi.com/f/nordic-q-a/34295/lf-hf-clock-configuration-with-softdevice</link><description>Hello, 
 I&amp;#39;m newbie with BLE and nrf52382. 
 I was looking in other questions but couldn&amp;#39;t find an answer for my problem. 
 Our board contains 2 external crystals: one of 32.768KHz connected to XL1 and XL2, and the other of 32MHz connected to XC1 and</description><dc:language>en-US</dc:language><generator>Telligent Community 13</generator><lastBuildDate>Tue, 22 May 2018 06:46:46 GMT</lastBuildDate><atom:link rel="self" type="application/rss+xml" href="https://devzone.nordicsemi.com/f/nordic-q-a/34295/lf-hf-clock-configuration-with-softdevice" /><item><title>RE: LF &amp; HF clock configuration with softdevice</title><link>https://devzone.nordicsemi.com/thread/132637?ContentTypeID=1</link><pubDate>Tue, 22 May 2018 06:46:46 GMT</pubDate><guid isPermaLink="false">137ad170-7792-4731-bb38-c0d22fbe4515:e4b33441-c464-409b-8d9d-864a7cf2ced7</guid><dc:creator>Joakim Jakobsen</dc:creator><description>&lt;p&gt;I&amp;#39;m glad it worked!&lt;/p&gt;
&lt;p&gt;Best regards, &lt;br /&gt;Joakim.&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item><item><title>RE: LF &amp; HF clock configuration with softdevice</title><link>https://devzone.nordicsemi.com/thread/132271?ContentTypeID=1</link><pubDate>Wed, 16 May 2018 12:23:08 GMT</pubDate><guid isPermaLink="false">137ad170-7792-4731-bb38-c0d22fbe4515:fad3a8f5-c46b-4fc6-81b2-3f1d3fc464a5</guid><dc:creator>Ran Ratson Kohavi</dc:creator><description>&lt;p&gt;Thanks alot for your reply.&lt;/p&gt;
&lt;p&gt;I&amp;#39;ve changed the RAM start adders from&amp;nbsp;0x20001720 to&amp;nbsp;0x20002068 and it solved the problem.&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item><item><title>RE: LF &amp; HF clock configuration with softdevice</title><link>https://devzone.nordicsemi.com/thread/132268?ContentTypeID=1</link><pubDate>Wed, 16 May 2018 12:16:23 GMT</pubDate><guid isPermaLink="false">137ad170-7792-4731-bb38-c0d22fbe4515:5cb26b90-35a0-4926-a451-cd38214615a8</guid><dc:creator>Joakim Jakobsen</dc:creator><description>&lt;p&gt;Hi!&lt;/p&gt;
&lt;p&gt;Error code 4;&amp;nbsp; &lt;br /&gt;NRF_ERROR_NO_MEM - No memory for operation.&lt;/p&gt;
&lt;p&gt;From the documentation: &lt;br /&gt;&lt;strong&gt;&amp;quot;BLE stack initialization&lt;/strong&gt;: A SoftDevice must be enabled with the required configuration parameters before it can be used. The default stack configuration can be customized with sd_ble_cfg_set before the SoftDevice is enabled. Most examples in the SDK use the default configuration with some modifications. When adapting an example, all of the default values may be overwritten. However, remember that changes might alter the size of the BLE stack RAM, which will change the application&amp;#39;s start RAM address. If you provide an incorrect RAM start address when calling &lt;span&gt;nrf_sdh_ble_enable&lt;/span&gt;, the function returns an error along with the new correct RAM start address. &amp;quot;&lt;/p&gt;
&lt;p&gt;Have you tried changing the RAM start address?&lt;/p&gt;
&lt;p&gt;Best regards, &lt;br /&gt;Joakim&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item><item><title>RE: LF &amp; HF clock configuration with softdevice</title><link>https://devzone.nordicsemi.com/thread/131859?ContentTypeID=1</link><pubDate>Mon, 14 May 2018 11:53:08 GMT</pubDate><guid isPermaLink="false">137ad170-7792-4731-bb38-c0d22fbe4515:796d51e3-1047-44a0-8ee0-be76605256b9</guid><dc:creator>Ran Ratson Kohavi</dc:creator><description>&lt;p&gt;Hello,&lt;/p&gt;
&lt;p&gt;After more debugging, I found that function&amp;nbsp;nrf_sdh_ble_enable() returns error code =4.&lt;/p&gt;
&lt;p&gt;&lt;pre class="ui-code" data-mode="c_cpp"&gt;static void ble_stack_init(void)
{
    ret_code_t err_code;

  
  /*
   * Before the delay was added, nrf_sdh_enable_request() got stuck
   */
  delay();
  
    err_code = nrf_sdh_enable_request();
    APP_ERROR_CHECK(err_code);

    // Configure the BLE stack using the default settings.
    // Fetch the start address of the application RAM.
    uint32_t ram_start = 0;
    err_code = nrf_sdh_ble_default_cfg_set(APP_BLE_CONN_CFG_TAG, &amp;amp;ram_start);
    APP_ERROR_CHECK(err_code);

    // Enable BLE stack.
    err_code = nrf_sdh_ble_enable(&amp;amp;ram_start);
    APP_ERROR_CHECK(err_code);

    // Register a handler for BLE events.
    NRF_SDH_BLE_OBSERVER(m_ble_observer, APP_BLE_OBSERVER_PRIO, ble_evt_handler, NULL);
}
&lt;/pre&gt;&lt;/p&gt;
&lt;p&gt;Here is the contents of the configuration file in my project:&lt;/p&gt;
&lt;p&gt;&lt;pre class="ui-code" data-mode="text"&gt;/*###ICF### Section handled by ICF editor, don&amp;#39;t touch! ****/
/*-Editor annotation file-*/
/* IcfEditorFile=&amp;quot;$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml&amp;quot; */
/*-Specials-*/
define symbol __ICFEDIT_intvec_start__ = 0x23000;
/*-Memory Regions-*/
define symbol __ICFEDIT_region_ROM_start__   = 0x23000;
define symbol __ICFEDIT_region_ROM_end__     = 0x7ffff;
define symbol __ICFEDIT_region_RAM_start__   = 0x20001720;
define symbol __ICFEDIT_region_RAM_end__     = 0x2000ffff;
export symbol __ICFEDIT_region_RAM_start__;
export symbol __ICFEDIT_region_RAM_end__;
/*-Sizes-*/
define symbol __ICFEDIT_size_cstack__   = 0x800;
define symbol __ICFEDIT_size_heap__     = 0x200;
/**** End of ICF editor section. ###ICF###*/

define memory mem with size = 4G;
define region ROM_region   = mem:[from __ICFEDIT_region_ROM_start__   to __ICFEDIT_region_ROM_end__];
define region RAM_region   = mem:[from __ICFEDIT_region_RAM_start__   to __ICFEDIT_region_RAM_end__];

define block CSTACK    with alignment = 8, size = __ICFEDIT_size_cstack__   { };
define block HEAP      with alignment = 8, size = __ICFEDIT_size_heap__     { };

initialize by copy { readwrite };
do not initialize  { section .noinit };

keep { section .intvec };
place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place in ROM_region   { readonly };
place in RAM_region   { readwrite,
                        block CSTACK,
                        block HEAP };&lt;/pre&gt;&lt;/p&gt;
&lt;p&gt;The SW calls&amp;nbsp;NVIC_SystemReset() which is in&amp;nbsp;app_error_fault_handler().&lt;/p&gt;
&lt;p&gt;Please help.&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item></channel></rss>