RE: [TIME URGENT] nRF24L01 not clearing FIFO buffers during read/write

BryanLavinParmenter — Thu, 24 May 2018 21:48:40 GMT

Hi Kenneth,

I actually figured out what our mistake was. It wasn't anything to do with the software. The micro controller that I am using only has a 16 byte FIFO for the SPI protocol, so the board was unable to read the 32 bytes from the nRF, and therefore would not clear the FIFO's on the nRF's. We increased the size of the SPI buffers and it worked immediately.

Best,

Bryan

RE: [TIME URGENT] nRF24L01 not clearing FIFO buffers during read/write

Kenneth — Thu, 24 May 2018 12:05:34 GMT

Can you try read RX payload width for the R_RX_PAYLOAD in the RX FIFO by using the R_RX_PL_WID command.

Note: Flush RX FIFO if the read value is larger than 32 bytes