SPIS data shifting

RE: SPIS data shifting

ovrebekk — Thu, 07 Jun 2018 06:45:58 GMT

Assuming your code goes to sleep you could try enabling constant latency mode. This will increase the current consumption, but should reduce the necessary delay between chip select and the SPI data.

Are you using a SoftDevice in your project or not?

If you use a SoftDevice you have to enable constant latency mode like this:

sd_power_mode_set(NRF_POWER_MODE_CONSTLAT);

If you don't use a SoftDevice you can enable it like this:

NRF_POWER->TASKS_CONSTLAT = 1;

Best regards
Torbjørn

RE: SPIS data shifting

arikyang — Wed, 06 Jun 2018 09:20:18 GMT

I am unable to change the code in the MCU, also it is not a Nordic platform.

RE: SPIS data shifting

ovrebekk — Wed, 06 Jun 2018 06:33:09 GMT

Are you unable to put in a delay because the SPIM hardware controls the CS pin, or because you are unable to change the code in the MCU?

RE: SPIS data shifting

arikyang — Mon, 04 Jun 2018 12:49:11 GMT

The problem is SPIM is in another system which I cannot put a delay between CS and clock.

RE: SPIS data shifting

arikyang — Mon, 04 Jun 2018 12:47:59 GMT

Have you measured the delay between CSN going low and the first bit being clocked out on the bus?

- no, haven't chance to measure.

Is the CPU on the slave side in sleep mode before the SPI interface is activated?

-Where can I know if CPU is in sleep? There is the idle_state_handle() in the main loop. Is that mean CPU will go to sleep?

As you can see in the specification there are some limits on how small the delay between CSN going low and the data being sent can be, depending on the power down mode used.

- The problem is SPIM is in another system which I cannot code a delay between CS and clock.

Also, what is the length and type of the SPI signal wires?
Do you have two devkits connected, or have you made custom hardware with signals on the PCB?

- It is two dev kits jump wires each other about 10cm.

RE: SPIS data shifting

Turbo J — Mon, 04 Jun 2018 11:59:39 GMT

Did you read chapter 32.6.2 "Serial Peripheral Interface Slave (SPIS) timing specifications"?

The SPIS needs a delay of 1000ns from the CS low transistion to the first CLK pulse - in CONSTLAT mode.

In low power mode this is even longer, since the HFINT oscillator must start up first.

RE: SPIS data shifting

ovrebekk — Mon, 04 Jun 2018 11:22:26 GMT

Have you measured the delay between CSN going low and the first bit being clocked out on the bus?

Is the CPU on the slave side in sleep mode before the SPI interface is activated?

As you can see in the specification there are some limits on how small the delay between CSN going low and the data being sent can be, depending on the power down mode used.

Also, what is the length and type of the SPI signal wires?
Do you have two devkits connected, or have you made custom hardware with signals on the PCB?

Best regards
Torbjørn

RE: SPIS data shifting

arikyang — Mon, 04 Jun 2018 01:16:38 GMT

2MHz

Yes, both sides are setting 0 mode.

I think SPIS peripheral is not response CS low quickly, sometimes MISO is still keeping HIGH when CS low and the clock has shaken.

The frequency roll down to 600KHz is more stable as my workaround.

RE: SPIS data shifting

ovrebekk — Fri, 01 Jun 2018 12:38:54 GMT

What clock frequency is the SPI running at?

Have you made sure to select the correct SPI mode (clock polarity and phase) both on the master and slave side?

Best regards
Torbjørn