RE: SPIS High power consumption

dbuijsma — Wed, 06 Jun 2018 20:19:46 GMT

Thanks Einar, that makes sense now. I can work around this by keeping the CS only active while data is being clocked in to reduce power to a minimum.

I have done some more digging on the forums and found that the nRF51 has a much more complete definition for power consumption. Specifically there's a chapter "8.3 Block resource requirements" in the Product Spec which makes it much more transparent what the mechanics in the SoC are doing. The nRF52 Product Spec does not contain this information. It's possible I missed it, but I could not find any documentation at all in the nRF52 product spec regarding DMA power-usage. I read that the SPIS peripheral takes 45uA so that's the number I use in my estimations. This number is completely meaningless without the mention of DMA, especially considering the fact I HAVE to use the DMA.

Just my 2 cents, I hope this will be considered as constructive feedback for the next nRF52 Product Spec revision.

RE: SPIS High power consumption

Einar Thorsrud — Wed, 06 Jun 2018 11:43:43 GMT

Hi Dirk,

The DMA mechanism itself has a significant current consumption of about 1.2 mA for the nRF52832. This is independent of the specific peripheral, and not counted in the electrical specification for the SPI peripheral (or any other). Please note that using DMA still improves the overall current consumption compared to not using DMA in most cases, as the nRF will be able to complete the transaction quicker, so that it can go to sleep as fast as possible.