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<?xml-stylesheet type="text/xsl" href="https://devzone.nordicsemi.com/cfs-file/__key/system/syndication/rss.xsl" media="screen"?><rss version="2.0" xmlns:dc="http://purl.org/dc/elements/1.1/" xmlns:slash="http://purl.org/rss/1.0/modules/slash/" xmlns:wfw="http://wellformedweb.org/CommentAPI/" xmlns:atom="http://www.w3.org/2005/Atom"><channel><title>The max amount of time can be spent in WDT interrupt</title><link>https://devzone.nordicsemi.com/f/nordic-q-a/35521/the-max-amount-of-time-can-be-spent-in-wdt-interrupt</link><description>Hi! As far as understood, there are only 2 clock cycles before the Watchdog timer reset occurs. Is there a way to change/set this to a different value? I need to write in the flash that watchdog is resetting my device. and 2clock cycles are not enough</description><dc:language>en-US</dc:language><generator>Telligent Community 13</generator><lastBuildDate>Tue, 19 Jun 2018 11:48:13 GMT</lastBuildDate><atom:link rel="self" type="application/rss+xml" href="https://devzone.nordicsemi.com/f/nordic-q-a/35521/the-max-amount-of-time-can-be-spent-in-wdt-interrupt" /><item><title>RE: The max amount of time can be spent in WDT interrupt</title><link>https://devzone.nordicsemi.com/thread/136740?ContentTypeID=1</link><pubDate>Tue, 19 Jun 2018 11:48:13 GMT</pubDate><guid isPermaLink="false">137ad170-7792-4731-bb38-c0d22fbe4515:200b7449-4baa-4e8e-bac2-889cb4da6c65</guid><dc:creator>Andy</dc:creator><description>&lt;p&gt;Oh, so then the RESETREAS register does work&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item><item><title>RE: The max amount of time can be spent in WDT interrupt</title><link>https://devzone.nordicsemi.com/thread/136723?ContentTypeID=1</link><pubDate>Tue, 19 Jun 2018 11:15:41 GMT</pubDate><guid isPermaLink="false">137ad170-7792-4731-bb38-c0d22fbe4515:75bacf43-4432-404b-b832-ed76237c371f</guid><dc:creator>Einar Thorsrud</dc:creator><description>&lt;p&gt;Referring to the table I linked to in my previous post, you can see the &amp;#39;x&amp;#39; in the intersection between the &amp;quot;Watchdog reset&amp;quot; and &amp;quot;Retained registers&amp;quot;. This indicates that the retained registers are reset by a watchdog reset. However, what this &lt;em&gt;really&lt;/em&gt; means is that the content is not guaranteed. In practice&amp;nbsp;it should work most of the time (perhaps always), as you write.&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item><item><title>RE: The max amount of time can be spent in WDT interrupt</title><link>https://devzone.nordicsemi.com/thread/136718?ContentTypeID=1</link><pubDate>Tue, 19 Jun 2018 11:04:56 GMT</pubDate><guid isPermaLink="false">137ad170-7792-4731-bb38-c0d22fbe4515:6b4b7eb1-d369-4590-a388-98aa0379b8ed</guid><dc:creator>Andy</dc:creator><description>&lt;p&gt;I don&amp;#39;t see anything there that says that it&amp;#39;s not guaranteed. At least it has been working consistently for me ever since I implemented it. The RESETREAS is not supported, that&amp;#39;s what I can see.&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item><item><title>RE: The max amount of time can be spent in WDT interrupt</title><link>https://devzone.nordicsemi.com/thread/136714?ContentTypeID=1</link><pubDate>Tue, 19 Jun 2018 11:00:25 GMT</pubDate><guid isPermaLink="false">137ad170-7792-4731-bb38-c0d22fbe4515:e17ca15d-4174-4c83-911c-b3c3ffbd99ee</guid><dc:creator>Einar Thorsrud</dc:creator><description>&lt;p&gt;That is true. But you should be aware that the content of&amp;nbsp;GPREGRET is not guaranteed after a watchdog reset (see &lt;a href="http://infocenter.nordicsemi.com/topic/com.nordic.infocenter.nrf52832.ps.v1.1/power.html?cp=2_1_0_17_7#unique_832471788"&gt;Reset behavior table&lt;/a&gt;). So a CRC or similar to validate it is recommended.&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item><item><title>RE: The max amount of time can be spent in WDT interrupt</title><link>https://devzone.nordicsemi.com/thread/136713?ContentTypeID=1</link><pubDate>Tue, 19 Jun 2018 10:48:09 GMT</pubDate><guid isPermaLink="false">137ad170-7792-4731-bb38-c0d22fbe4515:4856782c-127b-4bed-8583-581c04ee0923</guid><dc:creator>Andy</dc:creator><description>&lt;p&gt;You don&amp;#39;t need to write to flash. I write a code to&amp;nbsp;the GPREGRET in order to stay in bootloader after a watchdog reset. You could do the same for whatever purpose you need.&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item><item><title>RE: The max amount of time can be spent in WDT interrupt</title><link>https://devzone.nordicsemi.com/thread/136712?ContentTypeID=1</link><pubDate>Tue, 19 Jun 2018 10:44:09 GMT</pubDate><guid isPermaLink="false">137ad170-7792-4731-bb38-c0d22fbe4515:f7392ddc-70be-4b54-aaeb-ec6a369284a7</guid><dc:creator>Einar Thorsrud</dc:creator><description>&lt;p&gt;Hi,&lt;/p&gt;
&lt;p&gt;You have two &lt;em&gt;32 kHz&lt;/em&gt; clock cycles before the reset occurs. As you write, this means that there is no time for writing to flash, and it is not configurable.&lt;/p&gt;
&lt;p&gt;An alternative is that you could write data to a reserved RAM region instead, and check that region after every reset. The content of the RAM is not guaranteed through a watchdog reset, so you should write a CRC together with the data so that you can verify that the data is intact when you read it back after the reset.&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item></channel></rss>