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<?xml-stylesheet type="text/xsl" href="https://devzone.nordicsemi.com/cfs-file/__key/system/syndication/rss.xsl" media="screen"?><rss version="2.0" xmlns:dc="http://purl.org/dc/elements/1.1/" xmlns:slash="http://purl.org/rss/1.0/modules/slash/" xmlns:wfw="http://wellformedweb.org/CommentAPI/" xmlns:atom="http://www.w3.org/2005/Atom"><channel><title>Lowest power configuration for NFCT pins</title><link>https://devzone.nordicsemi.com/f/nordic-q-a/35523/lowest-power-configuration-for-nfct-pins</link><description>With our nRF53832 device we are not using NFC. 
 For the lowest power usage should I keep them as disabled NFC pins or change them to GPIO pins and drive them to the same logic level?</description><dc:language>en-US</dc:language><generator>Telligent Community 13</generator><lastBuildDate>Tue, 19 Jun 2018 12:12:57 GMT</lastBuildDate><atom:link rel="self" type="application/rss+xml" href="https://devzone.nordicsemi.com/f/nordic-q-a/35523/lowest-power-configuration-for-nfct-pins" /><item><title>RE: Lowest power configuration for NFCT pins</title><link>https://devzone.nordicsemi.com/thread/136746?ContentTypeID=1</link><pubDate>Tue, 19 Jun 2018 12:12:57 GMT</pubDate><guid isPermaLink="false">137ad170-7792-4731-bb38-c0d22fbe4515:5ee378c0-7dd5-4018-9fc8-a3fb65b6fd1d</guid><dc:creator>Martin Lesund</dc:creator><description>&lt;p&gt;Hi Matthew,&lt;/p&gt;
&lt;p&gt;It should not give a penalty on the current consumption when the NFCT peripheral is disabled. However; if the design does not use NFC, I would recommend using them as GPIOs HI-Z, input buffer disconnected.&lt;/p&gt;
&lt;p&gt;&amp;nbsp;&lt;/p&gt;
&lt;p&gt;&lt;span style="text-decoration:underline;"&gt;Copied from the &lt;a href="http://infocenter.nordicsemi.com/index.jsp?topic=%2Fcom.nordic.infocenter.nrf52832.ps.v1.1%2Fnfc.html&amp;amp;cp=2_1_0_41&amp;amp;anchor=concept_kmr_nxj_1s" target="_blank" rel="noopener noreferrer"&gt;NFCT documentation:&lt;/a&gt;&lt;/span&gt;&lt;/p&gt;
&lt;p&gt;&lt;em&gt;The pins dedicated to the NFC antenna function will have some limitation when the pins are configured for normal GPIO operation. The pin capacitance will be higher on those (refer to C&lt;sub&gt;PAD_NFC&lt;/sub&gt;&amp;nbsp;in the&amp;nbsp;&lt;a href="http://infocenter.nordicsemi.com/topic/com.nordic.infocenter.nrf52832.ps.v1.1/gpio.html#unique_1511470077"&gt;GPIO Electrical Specification&lt;/a&gt;&amp;nbsp;below), and some increased leakage current between the two pins is to be expected if they are used in GPIO mode, and are driven to different logical values. &lt;span style="background-color:#ffff99;"&gt;To save power the two pins should always be set to the same logical value whenever entering one of the device power saving modes&lt;/span&gt;. Please refer to I&lt;sub&gt;NFC_LEAK&lt;/sub&gt;&amp;nbsp;in&amp;nbsp;&lt;a href="http://infocenter.nordicsemi.com/topic/com.nordic.infocenter.nrf52832.ps.v1.1/gpio.html#unique_1511470077"&gt;GPIO Electrical Specification&lt;/a&gt;&amp;nbsp;for details.&lt;/em&gt;&lt;/p&gt;
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