https://devzone.nordicsemi.com/f/nordic-q-a/36481/i2c-interruptsHi. I have a problem to understand what is the difference in SFR registers IEN1 and INTEXP. Bit 2 in both of them is responsible for enabling 2-Wire completed interrupt, as stated in discreption. In addition, there is one more &quot;enabler&quot; - bit 5en-USTelligent Community 13Wed, 18 Jul 2018 18:04:59 GMThttps://devzone.nordicsemi.com/thread/140568?ContentTypeID=1Wed, 18 Jul 2018 18:04:59 GMT137ad170-7792-4731-bb38-c0d22fbe4515:ac4d36ba-c778-4d82-835c-b5e252747e9ebvgvova<p>Thank you, Simon.</p> <p>I had red the specification, of course. Misunderstanding comes from the fact, that &quot;enabling&quot; registers are connected in series. I thought that there was some hidden sense..</p> <p>nevertheless thanks for you reply.</p> <p>Best regasrds Vladimir.</p><div style="clear:both;"></div>https://devzone.nordicsemi.com/thread/140543?ContentTypeID=1Wed, 18 Jul 2018 14:25:29 GMT137ad170-7792-4731-bb38-c0d22fbe4515:2487c6df-89e3-4e81-b619-6bcf9fbaca0cSimon<p>The figure below gives some insight, the registers INTEXP and IEN1[2] are marked with red. In order to use WIRE2IRQ as source for the interrupts bit 2 in INTEXP and bit 2 in IEN1 needs to be set to 1.</p> <p>The register W2CON1 is concerned with configuration of the 2-Wire specifically, and the&nbsp;<a href="http://infocenter.nordicsemi.com/pdf/nRF24LE1_PS_v1.6.pdf">Product Specification</a>&nbsp;for nRFLE1 says the following about bit 5 in that register: &quot;Updates to the maskIrq configuration bit (W2CON1[5]) should be performed before transmission begins&quot;, and it should be assigned a value of 0 in order to enable interrupts.</p> <p></p> <p></p> <p><img alt=" " src="https://devzone.nordicsemi.com/resized-image/__size/640x480/__key/communityserver-discussions-components-files/4/6355.i2c.PNG" /></p> <p>Best regards Simon Iversen</p><div style="clear:both;"></div>