Effective impedance of ADC channel in single-shot mode with oversampling in burst mode

RE: Effective impedance of ADC channel in single-shot mode with oversampling in burst mode

zigenz — Fri, 20 Jul 2018 13:34:45 GMT

Thanks Haakon. I match up with your second result, but I think you may have made an error with your first result - I still get 0.982.

Anyway, regardless, it's all good. Thanks for your time.

RE: Effective impedance of ADC channel in single-shot mode with oversampling in burst mode

haakonsh — Fri, 20 Jul 2018 08:44:56 GMT

By my calculation that's Vo * 0.96 after 24µs at T = 1.38E-3, meaning that you've discharged 4% of Cext.

However you will charge somewhat during acquisition, so you should also calculate how much you will charge during those 24µs:

Vo(t) = Vo * (1 - e^(-t / Tc)) + Vo * e^(-t / Td), where Tc = charge time constant = 6E-2, and Td = discharge time constant = 1.38E-3

Vo(24µs) = Vo* ( (1 - e^(-24µs / 6E-2)) + e^(-24µs / 1.38E-3)) = Vo * 0.983

or 1.7% loss after 24µs, which is not that bad.

RE: Effective impedance of ADC channel in single-shot mode with oversampling in burst mode

zigenz — Fri, 20 Jul 2018 07:12:49 GMT

OK - so I had a think about this. Really, the question is how much of a voltage drop does the external 10nF buffer capacitor (Cext) cop for a single sample.

For the purpose of the analysis, I've assumed that:

1. Cext does not charge at all during an acquisition cycle.

2. Cext fully charges between acquisition cycles.

3. The resistance observed at the high-potential side of Cext is the combination of parasitic input resistance (~1Mohm), and ADC resistor network (160kohm) - both from SAADC elec spec part of datasheet => 138kohm.

If we sample for 3us and 8x oversampling, we are effectively drawing from Cext for 24us - the recovery gap in-between would charge Cext anyway, so this is the most conservative approach.

Using the standard capacitor discharge relationship V(t) = Voexp(-t/τ), where:

Vo = 1.8V (max), 1.2V (min)

t = 24us

τ = 1.38E-3 (RC => 138E3 * 10E-9)

This yields V(24us) = 0.982Vo, meaning we lose 1.8% of voltage during a single sample => acceptable error. The only other check becomes ensuring that Cext has sufficent time time charge up between samples, which is trivial.

So it looks like I answered my own question. If there are any glaring holes in my analysis, please advise!

- Z

RE: Effective impedance of ADC channel in single-shot mode with oversampling in burst mode

zigenz — Thu, 19 Jul 2018 15:00:16 GMT

Thanks haakonsh,

Based on the reference you provided, the MAXIMUM source resistance is 800kohm for a 40us sample time. I've actually included a 10nF Cext as shown in the second diagram of the app note, meaning I'm largely decoupled from the charging RC characteristic the ADC input (the basis for that table) - Cext will copy its charge straight onto Cinput, making the acquisition time table redundant in this case.

Please refer to the section titled "Choosing the sampling frequency" in the original app note link I provided. I want to understand how to calculate the effective impedance based on single-shot, burst mode oversampling.

-Z

RE: Effective impedance of ADC channel in single-shot mode with oversampling in burst mode

haakonsh — Thu, 19 Jul 2018 14:49:03 GMT

The Acquisition time is the time needed to fill the sample and hold capacitor. The larger the source resistance (6Mohm in your case) the longer the acquisition time you'll need to fill the capacitor. See Acquisition time. You should be fine with 40µs acquisition time at > 800kohm.

I also suggest you sample the battery voltage at peak current in order to determine the actual voltage level of the battery.