RE: How deterministic is it for PPI to detect a SPIS rx event and then control GPIOTE?

Sigurd — Mon, 13 Aug 2018 09:00:24 GMT

Hi,

The delay is here considered to be highly deterministic, and expected to be around 3 to 4 clock cycles@16MHz in constant latency mode. In Low power mode, there will be some additional delay and generally it might vary depending on the resources required by the peripheral where the task originated. Also keep in mind that the pin load capacitance and GPIO drive(high/low) will affect the GPIO rise/fall time. In total this seems to add up to 130 ns additional delay(4clock@16MHz + 130 = 380 ns). This is very similar to what others have measured.

[quote userid="62614" url="~/f/nordic-q-a/37293/how-deterministic-is-it-for-ppi-to-detect-a-spis-rx-event-and-then-control-gpiote"]And he'd like to know if PPI is deterministic and the delay is always 380ns as he observed. If so, he would not monitor READY_n line for 380ns after CS's deassertion.[/quote]

If it’s important to not miss the CS's/ READY_n's deassertion, it might be advisable to add some overhead/safety-margin to the 380 ns. One additional 16MHz clock tick (62.5 ns), or maybe two, should suffice.