<?xml version="1.0" encoding="UTF-8" ?>
<?xml-stylesheet type="text/xsl" href="https://devzone.nordicsemi.com/cfs-file/__key/system/syndication/rss.xsl" media="screen"?><rss version="2.0" xmlns:dc="http://purl.org/dc/elements/1.1/" xmlns:slash="http://purl.org/rss/1.0/modules/slash/" xmlns:wfw="http://wellformedweb.org/CommentAPI/" xmlns:atom="http://www.w3.org/2005/Atom"><channel><title>Timer 1ms with SD enabled</title><link>https://devzone.nordicsemi.com/f/nordic-q-a/3740/timer-1ms-with-sd-enabled</link><description>Hi 
 I&amp;#39;m trying to set up a 1ms tick timer using TIMER_1. In other words: every 1ms, I have to increment a tick counter, and to perform several operations. When SD is not enabled, the tick timer is working perfectly. The problems appear when the SD is</description><dc:language>en-US</dc:language><generator>Telligent Community 13</generator><lastBuildDate>Tue, 09 Sep 2014 08:03:55 GMT</lastBuildDate><atom:link rel="self" type="application/rss+xml" href="https://devzone.nordicsemi.com/f/nordic-q-a/3740/timer-1ms-with-sd-enabled" /><item><title>RE: Timer 1ms with SD enabled</title><link>https://devzone.nordicsemi.com/thread/13563?ContentTypeID=1</link><pubDate>Tue, 09 Sep 2014 08:03:55 GMT</pubDate><guid isPermaLink="false">137ad170-7792-4731-bb38-c0d22fbe4515:c736b2f4-50ff-45b5-9e0c-c5634bc86725</guid><dc:creator>Elena</dc:creator><description>&lt;p&gt;Thanks. I saw the resource availability, but I didn&amp;#39;t realize the about the latency.&lt;/p&gt;
&lt;p&gt;The latency I get is in the range of the expected latency, so I guess there&amp;#39;s no so much to do.&lt;/p&gt;
&lt;p&gt;Thanks again&lt;/p&gt;
&lt;p&gt;Regards,&lt;/p&gt;
&lt;p&gt;Elena&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item><item><title>RE: Timer 1ms with SD enabled</title><link>https://devzone.nordicsemi.com/thread/13562?ContentTypeID=1</link><pubDate>Fri, 05 Sep 2014 16:58:34 GMT</pubDate><guid isPermaLink="false">137ad170-7792-4731-bb38-c0d22fbe4515:268ed4ff-7452-478a-9949-6c69229025ce</guid><dc:creator>Nikita</dc:creator><description>&lt;p&gt;Read &amp;quot;11 Processor availability and interrupt latency&amp;quot; in S110_SoftDevice_Specification_v1 3.pdf.&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item></channel></rss>