RE: PPI + SoftDevice = HardFault?

Cedric Honnet — Sun, 02 Sep 2018 17:46:18 GMT

Hi Håkon!
Thanks a lot for your answer ;)
(sorry for the answer time, holidays made it longer than expected)

It looks like there was 2 problems:
- The priority was set to 3 already, but it was done after the softdevice was started and that was not good apparently!
- Once this was fixed, using the nrf_ppi_xxx() functions worked ;)

Thanks again for your help!

RE: PPI + SoftDevice = HardFault?

Håkon Alseth — Mon, 20 Aug 2018 07:42:08 GMT

Hi Cedric,

One of the changes from nRF51 to nRF52 is the amount of interrupt priorities available (cortex m0 vs cortex m4).

Here's the interrupt priority levels of the SoftDevice stack:

http://infocenter.nordicsemi.com/topic/com.nordic.infocenter.s140.sds/dita/softdevices/s130/processor_avail_interrupt_latency/exception_mgmt_sd.html?cp=2_3_2_0_15_1

You have two options to work around this hardfault:

1. Change the interrupt priority of the timer ISR to 5 or less, since SVC is handled in interrupt priority 4.

2. Instead of using the sd_ppi-API, you can call the NRF_PPI structure directly. This is because the PPI is an "open peripheral", meaning that the application can access it directly. The softdevice uses the hard-coded PPI channels as shown here.

Kind regards,

Håkon