<?xml version="1.0" encoding="UTF-8" ?>
<?xml-stylesheet type="text/xsl" href="https://devzone.nordicsemi.com/cfs-file/__key/system/syndication/rss.xsl" media="screen"?><rss version="2.0" xmlns:dc="http://purl.org/dc/elements/1.1/" xmlns:slash="http://purl.org/rss/1.0/modules/slash/" xmlns:wfw="http://wellformedweb.org/CommentAPI/" xmlns:atom="http://www.w3.org/2005/Atom"><channel><title>SWD, Reset line, and RTT</title><link>https://devzone.nordicsemi.com/f/nordic-q-a/37982/swd-reset-line-and-rtt</link><description>Hello, 
 We have an nrf51822 system where disconnecting the battery is problematic, and the sharing of the reset line between SWD and reset function has been a real source of problems for us. It&amp;#39;s time for me to understand the subtleties a little better</description><dc:language>en-US</dc:language><generator>Telligent Community 13</generator><lastBuildDate>Mon, 03 Sep 2018 07:35:11 GMT</lastBuildDate><atom:link rel="self" type="application/rss+xml" href="https://devzone.nordicsemi.com/f/nordic-q-a/37982/swd-reset-line-and-rtt" /><item><title>RE: SWD, Reset line, and RTT</title><link>https://devzone.nordicsemi.com/thread/146892?ContentTypeID=1</link><pubDate>Mon, 03 Sep 2018 07:35:11 GMT</pubDate><guid isPermaLink="false">137ad170-7792-4731-bb38-c0d22fbe4515:ffa22bd5-7813-480e-8928-c1f8fe4520f4</guid><dc:creator>Kenneth</dc:creator><description>&lt;p&gt;Hello,&lt;/p&gt;
&lt;p&gt;There is no specific relationship between the two pins, other than they share an SWD interface. Have you tried my suggestion yet?&amp;nbsp;&lt;/p&gt;
&lt;p&gt;The 1kohm pull down resistor on SWDCLK should already be part of the reference schematic, so the only thing &amp;quot;new&amp;quot; compared to the reference&amp;nbsp;schematic in my suggestion should be to add a 1Mohm pull down on SWDIO.&lt;/p&gt;
&lt;p&gt;Best regards,&lt;br /&gt;Kenneth&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item><item><title>RE: SWD, Reset line, and RTT</title><link>https://devzone.nordicsemi.com/thread/146583?ContentTypeID=1</link><pubDate>Thu, 30 Aug 2018 17:44:55 GMT</pubDate><guid isPermaLink="false">137ad170-7792-4731-bb38-c0d22fbe4515:7131e2e3-ad36-44a3-a2e7-0d12a9a51354</guid><dc:creator>Jandyman</dc:creator><description>&lt;p&gt;Thanks. On the second question, I know I&amp;#39;m getting a proper reset signal on the reset line because I&amp;#39;ve looked at it on the scope. Remember that VDD is high the entire time in this scenario since we are connected to a battery. If I take the unit apart and disconnect and reconnect the battery, I can get back into debug mode. But your comment about the other line is interesting. Does getting back into debug mode from normal mode involve using &lt;em&gt;both&lt;/em&gt; pins in concert?&lt;/p&gt;
&lt;p&gt;The problem we&amp;#39;ve been fighting is that I need to set the NRF_POWER-&amp;gt;Reset pin&amp;nbsp;in code&amp;nbsp;for release code so the reset pin behaves normally, but &lt;em&gt;sometimes&lt;/em&gt; I can&amp;#39;t get back to debug mode once this is done, and I can&amp;#39;t program the chip either. The battery disconnect seems to be the only thing that works at that point. I haven&amp;#39;t figured out what the exact trigger for this is, because it doesn&amp;#39;t &lt;em&gt;always&lt;/em&gt; get wedged. It is very mysterious. And it is becoming a giant problem&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item><item><title>RE: SWD, Reset line, and RTT</title><link>https://devzone.nordicsemi.com/thread/146578?ContentTypeID=1</link><pubDate>Thu, 30 Aug 2018 16:43:11 GMT</pubDate><guid isPermaLink="false">137ad170-7792-4731-bb38-c0d22fbe4515:22e08021-5702-43d6-bc03-83b7089b87d2</guid><dc:creator>Kenneth</dc:creator><description>&lt;p&gt;Hi,&lt;/p&gt;
[quote user=""] I have been doing this programmatically in my code by modifying the reset register in the power peripheral, but it would be preferable to do this with a programming tool instead. Is this possible?[/quote]
&lt;p&gt;That is the way to go. You should enable pin reset by writing to the NRF_POWER-&amp;gt;RESET register in beginning of main(). This will ensure that pin reset always works (even in debug mode). The only way to exit debug mode is power cycle or pin reset. The only way to enter debug mode is a clock cycle on SWDCLK.&lt;/p&gt;
[quote user=""]but some times the chip gets wedged and we have to take things apart and disconnect the battery to restore function.[/quote]
&lt;p&gt;Sounds like you are having issue to get a proper reset. Try to connect a 1Mohm between SWDIO and GND and let me know if you see the problem again. This should act as an additional reset source if you are having VDD connection or slow VDD ramp up issues. Also add a 1kohm between SWDCLK and GND if you haven&amp;#39;t already.&lt;/p&gt;
[quote user=""]Is it possible to tap into SWD RTT without &amp;quot;disturbing&amp;quot; a running program? And if so, what tool would I use to do this?[/quote]
&lt;p&gt;Unfortunately no.&lt;/p&gt;
&lt;p&gt;Best regards,&lt;br /&gt;Kenneth&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item></channel></rss>