Question on QSPI(NAND) & SPI

RE: Question on QSPI(NAND) & SPI

Constantin — Thu, 06 Aug 2020 14:17:33 GMT

Any progress in the meantime?

RE: Question on QSPI(NAND) & SPI

Mihal — Fri, 01 Feb 2019 01:00:12 GMT

as i can see W25N01GVZEIG has "read status register" command and it's NAND. but i still don't know how to work with it properly

RE: Question on QSPI(NAND) & SPI

Jong yoon lee — Wed, 12 Sep 2018 14:58:58 GMT

Any update?

RE: Question on QSPI(NAND) & SPI

Jong yoon lee — Fri, 31 Aug 2018 15:07:15 GMT

Thank you for your thoughtful answer.

Regarding communicating with NAND flash, I was concerned about the status check that is being done on a write and read operation.

QSPI does a `Read Register Status` - 05h to do a Memory status check before a read/write/erase. The peripheral will pull this register until it is in the state needed. However, this is only a feature in a NOR flash and non of the NAND flash I looked into doesn't support the `Read Register Status` command.
Is there a way to bypass this memory status check?

RE: Question on QSPI(NAND) & SPI

Andreas — Fri, 31 Aug 2018 13:50:03 GMT

Hi,

First, you're referring to an old version of the datasheet. See v1 instead.

NAND flash should be possible to use as far as I know. This is just the underlying technology, if the interface is compatible it should not matter.

We do not have current consumption data for this unfortunately. Still, at this frequency this is something that is wildly dependent on trace and load capacitance, which you therefore would have to measure in your own board .

Regarding the formula, should there not be only 'bits' in the numerator? This leaves time needed to transfer e.g. 5000 bits, which when multiplied with the current draw leads to charge (mAh) used in the transaction.

Best regards,

Andreas