<?xml version="1.0" encoding="UTF-8" ?>
<?xml-stylesheet type="text/xsl" href="https://devzone.nordicsemi.com/cfs-file/__key/system/syndication/rss.xsl" media="screen"?><rss version="2.0" xmlns:dc="http://purl.org/dc/elements/1.1/" xmlns:slash="http://purl.org/rss/1.0/modules/slash/" xmlns:wfw="http://wellformedweb.org/CommentAPI/" xmlns:atom="http://www.w3.org/2005/Atom"><channel><title>NVMC timing</title><link>https://devzone.nordicsemi.com/f/nordic-q-a/3997/nvmc-timing</link><description>I&amp;#39;m currently designing a system that requires Nonvolatile memory. Whilst I can accept the 43uS delay to write a word to flash memory. My concern is that it is entirely possible in the operation of the device to erase a flash page. This will take 21ms</description><dc:language>en-US</dc:language><generator>Telligent Community 13</generator><lastBuildDate>Fri, 30 Jan 2015 01:44:40 GMT</lastBuildDate><atom:link rel="self" type="application/rss+xml" href="https://devzone.nordicsemi.com/f/nordic-q-a/3997/nvmc-timing" /><item><title>RE: NVMC timing</title><link>https://devzone.nordicsemi.com/thread/14359?ContentTypeID=1</link><pubDate>Fri, 30 Jan 2015 01:44:40 GMT</pubDate><guid isPermaLink="false">137ad170-7792-4731-bb38-c0d22fbe4515:193bf1a2-f1c8-41ee-a8e0-b418ff8a7eef</guid><dc:creator>michael.crapse</dc:creator><description>&lt;p&gt;As long as you use the functions sd_flash_page_erase and sd_flash_write the bluetooth stack will not be affected by it. It will register with the soft device that an event requiring 21ms is required. The soft device will eventually be able to block out enough time to do this operation(might be a long time depending on the traffic you&amp;#39;re putting through your radio)&lt;/p&gt;
&lt;p&gt;Before you start another operation, be sure to wait for a flash success event as it will not be a guaranteed time before it writes the flash.&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item><item><title>RE: NVMC timing</title><link>https://devzone.nordicsemi.com/thread/14355?ContentTypeID=1</link><pubDate>Tue, 14 Oct 2014 15:11:50 GMT</pubDate><guid isPermaLink="false">137ad170-7792-4731-bb38-c0d22fbe4515:8242d3b3-3c5f-4261-a87f-cabd71653a43</guid><dc:creator>michael.crapse</dc:creator><description>&lt;p&gt;Still hasn&amp;#39;t been answered..&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item><item><title>RE: NVMC timing</title><link>https://devzone.nordicsemi.com/thread/14358?ContentTypeID=1</link><pubDate>Mon, 06 Oct 2014 21:40:06 GMT</pubDate><guid isPermaLink="false">137ad170-7792-4731-bb38-c0d22fbe4515:bfcebe70-6689-4788-a410-422cf4b37f30</guid><dc:creator>Nguyen Hoan Hoang</dc:creator><description>&lt;p&gt;Thanks for the info.  I could understand the CPU halt for erase all but for page why would it halt to CPU.  Even CPU halt, your I/O still work and so the radio.  I have used it in an acquisition system with 20 i/o begin monitor and operate at the same time as transmitting data over ble.  We had issue with, just do not use GPIOTE.  I found that GPIOTE latency was to high.  It didn&amp;#39;t work in our system.  We use direct pin change interrupt for that.&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item><item><title>RE: NVMC timing</title><link>https://devzone.nordicsemi.com/thread/14357?ContentTypeID=1</link><pubDate>Mon, 06 Oct 2014 21:28:04 GMT</pubDate><guid isPermaLink="false">137ad170-7792-4731-bb38-c0d22fbe4515:1feec798-c4ca-4d97-933b-0d69bb7daf3f</guid><dc:creator>michael.crapse</dc:creator><description>&lt;p&gt;According to the nrf51_Series_Reference_Manual_v2.1.pdf on page 14, under section 5.1.5.
&amp;quot;The time it takes to erase a page is specified by tPAGEERASE in the product specification. The CPU is halted while the NVMC performs the erase operation.&amp;quot;&lt;/p&gt;
&lt;p&gt;Looking in the product specification it shows 21ms for a page erase. My understanding of the Softdevice would be that this complete and utter blocking of the CPU would be unacceptable in the central role.&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item><item><title>RE: NVMC timing</title><link>https://devzone.nordicsemi.com/thread/14356?ContentTypeID=1</link><pubDate>Mon, 06 Oct 2014 21:21:43 GMT</pubDate><guid isPermaLink="false">137ad170-7792-4731-bb38-c0d22fbe4515:b25cc8d9-37a7-4a57-bf49-0a41292dea71</guid><dc:creator>Nguyen Hoan Hoang</dc:creator><description>&lt;p&gt;To my knowledge, Pstorage is non blocking.  Flash write is hardware.  The software only issues the command and then poll it status for completion or wait for completion interrupt (depends if interrupt is implemented or not).  It should not affect any time critical path.&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item></channel></rss>