RE: nrf24l01+ Auto acknowledge problem

Håkon Alseth — Mon, 07 Jan 2019 08:09:16 GMT

I do not see anything standing out wrt. your configuration. As long as you also set the payload width to 32 and the RF channel to 42 on the PRX side as well, it should work.

Do you have more than one module that you see this issue on? Could you post pictures of the modules that you use?

[quote]This is actually post of the someone at other forums, but the my situation %100 same[/quote]

Could you post the link to this?

RE: nrf24l01+ Auto acknowledge problem

YDoc — Fri, 04 Jan 2019 15:16:27 GMT

// Transmitter

uint8_t nrf_tx_addr[ ] ={
0xE8,
0xE8,
0xE8,
0xE8,
0xE8
};

uint8_t nrf_rx_addr_p0[ ] ={
0xE8,
0xE8,
0xE8,
0xE8,
0xE8
};

uint8_t nrf_rx_addr_p1[ ] ={
0xC1,
0xC1,
0xC1,
0xC1,
0xC1
};

nrf_WriteRegister(nrf_reg_SETUP_AW,0x03); // Address width adjusted to 5 bytes
nrf_WriteRegister(nrf_reg_EN_AA,0x03); // Auto ACK enabled for only data pipe 0,1

nrf_WriteRegister(nrf_reg_EN_RXADDR,0x03); // RX Pipelines enabled( 0 and 1 )

nrf_WriteRegister(nrf_reg_rx_pw_P0,32); // PAYLOAD width of P0 adjusted to 32 bytes
nrf_WriteRegister(nrf_reg_rx_pw_P1,32); // PAYLOAD width of P1 adjusted to 32 bytes

nrf_MultiWriteRegister(nrf_reg_Tx_ADDR,nrf_tx_addr,5); // Transmit address
nrf_MultiWriteRegister(nrf_reg_RX_ADDR_P0,nrf_rx_addr_p0,5); // Receive address of pipeline 0
nrf_MultiWriteRegister(nrf_reg_RX_ADDR_P1,nrf_rx_addr_p1,5); // Receive address of pipeline 1

nrf_WriteRegister(nrf_reg_SETUP_RETR,0x28); // 750uS Auto retransmit delay , 8 max auto retransmit
nrf_WriteRegister(nrf_reg_RF_SETUP,0x0E); // Output Power = 0 dBm , Datarate = 2 Mbps
nrf_WriteRegister(nrf_reg_RF_CH,0x2A); // Frequency band = 2400 MHz + 42 = 2442 MHz

// For Receiver same configuration with address setting at below

uint8_t nrf_tx_addr[] ={
0xC1,
0xC1,
0xC1,
0xC1,
0xC1
};

uint8_t nrf_rx_addr_p0[] ={
0xC1,
0xC1,
0xC1,
0xC1,
0xC1
};

uint8_t nrf_rx_addr_p1[] ={
0xE8,
0xE8,
0xE8,
0xE8,
0xE8
};

RE: nrf24l01+ Auto acknowledge problem

Håkon Alseth — Fri, 04 Jan 2019 09:21:58 GMT

Hi,

Could you post the configuration on both ends?

It is very important that this is equal on both sides.

Kind regards,

Håkon