nrf52832 spi (PSEL.SCK)

RE: nrf52832 spi (PSEL.SCK)

Jared — Thu, 07 Mar 2019 15:27:45 GMT

Again, I don't think the problem is from the initializing of the GPIO as the previous project didn't have the gaps when i initialized the GPIO. I first observed the gaps when the last_valid_cmd[0] = 0 was included.

RE: nrf52832 spi (PSEL.SCK)

yanli_1226 — Thu, 28 Feb 2019 10:21:25 GMT

there is the same problem in spi sck when I use the nRF5_SDK_15.0.0_a53641a, I use the project in \nRF5_SDK_15.0.0_a53641a\examples\peripheral\spi\pca10040\blank\arm5_no_packs, and alternate three files: main.c, nrf_drv_spi.c, nrf_drv_spi.h. main.c is just like below:

devzone.nordicsemi.com/.../spi_5F00_test.rar devzone.nordicsemi.com/.../5226.nrf_5F00_drv_5F00_spi.c

devzone.nordicsemi.com/.../7215.nrf_5F00_drv_5F00_spi.h

devzone.nordicsemi.com/.../81441.main.c

RE: nrf52832 spi (PSEL.SCK)

Jared — Fri, 15 Feb 2019 08:43:46 GMT

Try:

spi_master_init();
nrf_gpio_cfg_output(30); // if pin30 is not set output and set1/clear0,spi sck is not right
nrf_gpio_pin_clear(30);
//last_valid_cmd[0] = 0;

and see if the issue still appears.

You can download our SDK from here

Best regards

Jared

RE: nrf52832 spi (PSEL.SCK)

yanli_1226 — Fri, 15 Feb 2019 08:14:05 GMT

config like this:

spi_master_init();
nrf_gpio_cfg_output(30); // if pin30 is not set output and set1/clear0,spi sck is not right
nrf_gpio_pin_clear(30);
//last_valid_cmd[0] = 0;

or config like this:

spi_master_init();
//nrf_gpio_cfg_output(30); // if pin30 is not set output and set1/clear0,spi sck is not right
//nrf_gpio_pin_clear(30);
last_valid_cmd[0] = 0;

there are not gaps between every 8clocks, only config like this:

spi_master_init();
nrf_gpio_cfg_output(30); // if pin30 is not set output and set1/clear0,spi sck is not right
nrf_gpio_pin_clear(30);
last_valid_cmd[0] = 0;

there are gaps between every 8clocks

RE: nrf52832 spi (PSEL.SCK)

yanli_1226 — Fri, 15 Feb 2019 06:47:46 GMT

how to get SDK version，I download the example from ARM/pack

RE: nrf52832 spi (PSEL.SCK)

Jared — Wed, 13 Feb 2019 11:44:49 GMT

I meant to write: Which SDK Version are you using? Have you tried commenting out the line last_valid_cmd[0] = 0 and see if the issue persists?

RE: nrf52832 spi (PSEL.SCK)

yanli_1226 — Wed, 13 Feb 2019 07:46:53 GMT

I use the example installed in keil/ARM/pack

RE: nrf52832 spi (PSEL.SCK)

Jared — Thu, 07 Feb 2019 08:57:03 GMT

It doesn't seem that it is the initialization of the GPIO that is causing the issue but rather the initialization of the last_valid_cmd[0] = 0. Which SDK are you using?

RE: nrf52832 spi (PSEL.SCK)

yanli_1226 — Tue, 22 Jan 2019 03:30:14 GMT

Thanks, the code is just as bellow:

devzone.nordicsemi.com/.../nrf52832_5F00_SPI_5F00_VTEST.rar

In main.c , if I comment the following, there are not gaps between every 8 SPI SCK

//nrf_gpio_cfg_output(30); // if pin30 is not set output and set1/clear0,spi sck is not right
//nrf_gpio_pin_clear(30);
//last_valid_cmd[0] = 0;

If I not comment the following,there are gaps between every 8 SPI SCK

nrf_gpio_cfg_output(30); // if pin30 is not set output and set1/clear0,spi sck is not right
nrf_gpio_pin_clear(30);
last_valid_cmd[0] = 0;

that's strange, I don't know what's the matter?

RE: nrf52832 spi (PSEL.SCK)

Jared — Mon, 21 Jan 2019 08:52:56 GMT

I find this very strange. Could you share your code so I could try to reproduce the error?

RE: nrf52832 spi (PSEL.SCK)

yanli_1226 — Wed, 16 Jan 2019 03:11:10 GMT

the picture is SPI SCK, I want the SPI SCK to have gaps between every 8 clock, so I use NRF_SPIM0->TXD.MAXCNT = 1; NRF_SPIM0->RXD.MAXCNT = 1;

P0.30 is an IO, not used as an SPI pin, but I find that , if I not config P0.30 as a output pin, there are not gaps between every 8 clock, just like the picture shows. IF I config P0.30 as a output pin(I config P0.30 like this:nrf_gpio_cfg_output(30); nrf_gpio_pin_clear(30);), there are gaps between every 8 clock just as what I want.

the question is :P0.30 is not used as an SPI pin, why it influences the SPI SCK Waveform。the SPI code is just like bellow:

RE: nrf52832 spi (PSEL.SCK)

Jared — Mon, 14 Jan 2019 14:32:38 GMT

Hi,

I'm not sure i understand your problem.

What do you mean by output pin? The data pin for SPI? A GPIO pin?
What is shown in the picture? The clock signal? The data line?
What is meant by not configuring P0.30?

Best regards

Jared