problems with SPI on nRF9160 and Zephyr

RE: problems with SPI on nRF9160 and Zephyr

RodWatt — Thu, 23 May 2019 18:58:44 GMT

Thanks Jeff

RE: problems with SPI on nRF9160 and Zephyr

Jeff Seaman — Mon, 22 Apr 2019 11:33:22 GMT

I have not worked with this in some time. I was running the loopback test.

check the configuration of secure boot and also I have had to add some peripherals in the secure boot source code to enable them so make sure the spi is set in that and the secure boot prj.conf files matches what you are using in the program prj.conf file.

also print out the device value once you have configured it and make sure it is not 0. a zero value shows the peripheral is not avilable.

RE: problems with SPI on nRF9160 and Zephyr

RodWatt — Fri, 19 Apr 2019 21:57:26 GMT

Hi Jeff,

Did you manage to get this working? I am also trying to get the SPI interface up and running. I can run the basic SPI loopback test but am unable to get access to and SPI peripheral. I am trying to get the the BME280 code working, works with I2C but I can't get it to work with SPI. Anyway, any tips you can share would be appreciated. Thanks, Rod

RE: problems with SPI on nRF9160 and Zephyr

Håkon Alseth — Fri, 01 Feb 2019 11:29:57 GMT

There's a very simplistic SPI3 example linked in this case, if anyone is interested:

https://devzone.nordicsemi.com/f/nordic-q-a/43185/unable-to-modify-nrf9160dk-asset_tracker-to-add-spi-slave-functionality/169035#169035

Kind regards,

Håkon

RE: problems with SPI on nRF9160 and Zephyr

Jeff Seaman — Fri, 25 Jan 2019 12:42:10 GMT

Hi Jan

I just took one of the Zephyr samples and started to adapt to see how things work. Once I got some activity my plan was to make it work with my chip.

/*
 * Copyright (c) 2016 Intel Corporation
 *
 * SPDX-License-Identifier: Apache-2.0
 */

#include <errno.h>
#include <zephyr.h>
#include <misc/printk.h>
#include <device.h>
#include <spi.h>

/**
 * @file Sample app using the Fujitsu MB85RS64V FRAM through SPI.
 */

#define MB85RS64V_MANUFACTURER_ID_CMD 0x9f
#define MB85RS64V_WRITE_ENABLE_CMD 0x06
#define MB85RS64V_READ_CMD 0x03
#define MB85RS64V_WRITE_CMD 0x02
#define MAX_USER_DATA_LENGTH 1024

static u8_t data[MAX_USER_DATA_LENGTH], cmp_data[MAX_USER_DATA_LENGTH];

static int mb85rs64v_access(struct device *spi, struct spi_config *spi_cfg,
			    u8_t cmd, u16_t addr, void *data, size_t len)
{
	u8_t access[3];
	struct spi_buf bufs[] = {
		{
			.buf = access,
		},
		{
			.buf = data,
			.len = len
		}
	};
	struct spi_buf_set tx = {
		.buffers = bufs
	};

	access[0] = cmd;

	if (cmd == MB85RS64V_WRITE_CMD || cmd == MB85RS64V_READ_CMD) {
		access[1] = (addr >> 8) & 0xFF;
		access[2] = addr & 0xFF;

		bufs[0].len = 3;
		tx.count = 2;

		if (cmd == MB85RS64V_READ_CMD) {
			struct spi_buf_set rx = {
				.buffers = bufs,
				.count = 2
			};

			return spi_transceive(spi, spi_cfg, &tx, &rx);
		}
	} else {
		tx.count = 1;
	}

	return spi_write(spi, spi_cfg, &tx);
}


static int mb85rs64v_read_id(struct device *spi, struct spi_config *spi_cfg)
{
	u8_t id[4];
	int err;

	err = mb85rs64v_access(spi, spi_cfg,
			       MB85RS64V_MANUFACTURER_ID_CMD, 0, &id, 4);
	if (err) {
		printk("Error during ID read\n");
		return -EIO;
	}

	if (id[0] != 0x04) {
		return -EIO;
	}

	if (id[1] != 0x7f) {
		return -EIO;
	}

	if (id[2] != 0x03) {
		return -EIO;
	}

	if (id[3] != 0x02) {
		return -EIO;
	}

	return 0;
}

static int write_bytes(struct device *spi, struct spi_config *spi_cfg,
		       u16_t addr, u8_t *data, u32_t num_bytes)
{
	int err;

	/* disable write protect */
	err = mb85rs64v_access(spi, spi_cfg,
			       MB85RS64V_WRITE_ENABLE_CMD, 0, NULL, 0);
	if (err) {
		printk("unable to disable write protect\n");
		return -EIO;
	}

	/* write cmd */
	err = mb85rs64v_access(spi, spi_cfg,
			       MB85RS64V_WRITE_CMD, addr, data, num_bytes);
	if (err) {
		printk("Error during SPI write\n");
		return -EIO;
	}

	return 0;
}

static int read_bytes(struct device *spi, struct spi_config *spi_cfg,
		      u16_t addr, u8_t *data, u32_t num_bytes)
{
	int err;

	/* read cmd */
	err = mb85rs64v_access(spi, spi_cfg,
			       MB85RS64V_READ_CMD, addr, data, num_bytes);
	if (err) {
		printk("Error during SPI read\n");
		return -EIO;
	}

	return 0;
}

void main(void)
{
	struct device *spi;
        struct device *gpio_dev;
	struct spi_config spi_cfg;
        struct spi_cs_control cs_control;
	int err;

	printk("fujitsu FRAM example application\n");

	spi = device_get_binding("SPI_3");
	if (!spi) {
		printk("Could not find SPI 3 driver\n");
		return;
	}else{
                printk("SPI_3 %x\n",spi);
        }

        gpio_dev = device_get_binding("GPIO_0");
        if(!gpio_dev) {
                printk("could not find GPIO device\n");
                return;
        }
        cs_control.delay = 0;
        cs_control.gpio_dev = gpio_dev;
        cs_control.gpio_pin = 22;
	spi_cfg.operation = SPI_WORD_SET(8);
	spi_cfg.frequency = 256000;
        spi_cfg.cs = &cs_control; 

while(1){
	err = mb85rs64v_read_id(spi, &spi_cfg);
	if (err) {
		printk("Could not verify FRAM ID\n");
		
	}
           }

	
}

If it would help I can email you the entire project. Nothing private in it.

RE: problems with SPI on nRF9160 and Zephyr

Jan Tore Guggedal — Fri, 25 Jan 2019 09:19:43 GMT

Hi Jeff,

It would be useful to see what's going on in your main.c files. That would make it easiuer to reproduce your setup locally.

RE: problems with SPI on nRF9160 and Zephyr

Jeff Seaman — Thu, 24 Jan 2019 12:59:52 GMT

Have you tried anything with the SPI. I also tryed the SPI under Zephyr on the nRF52840 with no results.

RE: problems with SPI on nRF9160 and Zephyr

SindreSB — Thu, 24 Jan 2019 08:33:43 GMT

I'd love to get a sample of this as well

RE: problems with SPI on nRF9160 and Zephyr

Jeff Seaman — Mon, 21 Jan 2019 16:39:28 GMT

Martin

I tried setting the project up on SPI 3 and configuring secure boot.

the prj.conf for secure boot

CONFIG_TRUSTED_EXECUTION_SECURE=y
CONFIG_UART_1_NRF_UARTE=y
CONFIG_SPI_3_NRF_SPIM=y
# needed to get the NRF_UARTE2 define
CONFIG_UART_2_NRF_UARTE=y

the overlay for secure boot

/* needed to get the NRF_UARTE2 defined */
&uart1{
	current-speed = <38400>;
	tx-pin = <24>;
	rx-pin = <25>;
	cts-pin = <27>;
	rts-pin = <28>;

};

&uart2 {
	current-speed = <1000000>;
	status = "ok";
	tx-pin = <18>;
	rx-pin = <17>;
	rts-pin = <19>;
	cts-pin = <21>;
};

&spi3 {
        status = "ok";
        sck-pin = <26>;
        mosi-pin = <27>;
        miso-pin = <28>;
        spi-max-frequency = <4000000>;
};

the prj.conf file for the application

# General config
CONFIG_NEWLIB_LIBC=y

# Trusted execution
CONFIG_TRUSTED_EXECUTION_NONSECURE=y


CONFIG_SERIAL=y
CONFIG_UART_INTERRUPT_DRIVEN=y

CONFIG_GPIO=y

CONFIG_SPI=y
CONFIG_SPI_NRFX=y
CONFIG_SPI_3=y
CONFIG_SPI_3_NRF_SPIM=y

CONFIG_PRINTK=y
CONFIG_HEAP_MEM_POOL_SIZE=256
CONFIG_ASSERT=y

the overlay for the application

&spi3 {
        status = "ok";
        sck-pin = <26>;
        mosi-pin = <27>;
        miso-pin = <28>;
        spi-max-frequency = <4000000>;
};

I am still not seeing any activity on the SPI clock pin

I will try your next suggestion

Thanks for the Help

RE: problems with SPI on nRF9160 and Zephyr

Martin Lesund — Mon, 21 Jan 2019 14:57:39 GMT

Hi Jeff,

When working with nrf9160 samples, it has to be built as a non-secure firmware image.
So that means that you need to add:

CONFIG_TRUSTED_EXECUTION_NONSECURE=y

in the prj.conf file for your application. I also recommend that you copy your .overlay file and add it in the secure_boot sample and build/flash that again.

(I assume that you are already using the nrfx_spi driver)

We do not have a sample for this yet, but I can see if I can make something for you if the pointers aren't enough.