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<?xml-stylesheet type="text/xsl" href="https://devzone.nordicsemi.com/cfs-file/__key/system/syndication/rss.xsl" media="screen"?><rss version="2.0" xmlns:dc="http://purl.org/dc/elements/1.1/" xmlns:slash="http://purl.org/rss/1.0/modules/slash/" xmlns:wfw="http://wellformedweb.org/CommentAPI/" xmlns:atom="http://www.w3.org/2005/Atom"><channel><title>How to reset TWI during async operation</title><link>https://devzone.nordicsemi.com/f/nordic-q-a/42876/how-to-reset-twi-during-async-operation</link><description>Hi, 
 I have setup TWI peripheral for async transfers via IRQ and callback. After firing the transfer operation, I feel uneasy about having no control until the interrupt happens. Sometimes while playing with TWI wires I&amp;#39;ve been able to lock the bus,</description><dc:language>en-US</dc:language><generator>Telligent Community 13</generator><lastBuildDate>Wed, 23 Jan 2019 17:44:56 GMT</lastBuildDate><atom:link rel="self" type="application/rss+xml" href="https://devzone.nordicsemi.com/f/nordic-q-a/42876/how-to-reset-twi-during-async-operation" /><item><title>RE: How to reset TWI during async operation</title><link>https://devzone.nordicsemi.com/thread/167459?ContentTypeID=1</link><pubDate>Wed, 23 Jan 2019 17:44:56 GMT</pubDate><guid isPermaLink="false">137ad170-7792-4731-bb38-c0d22fbe4515:f49d1cd2-8c63-49ad-a3cd-b735eeb0beb1</guid><dc:creator>Kenneth</dc:creator><description>&lt;p&gt;Hi,&lt;/p&gt;
&lt;p&gt;What you describe is something that happens during prototype development, while doing various debugging etc. However once mounted on the same PCB and the firmware is tested, I am not aware of anyone actually taking any specific precautions for twi transfers. What you describe I would say is more common for UART transfers, however feel free to add safety mechanisms as you like.&lt;/p&gt;
&lt;p&gt;Best regards,&lt;br /&gt;Kenneth&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item></channel></rss>