SPI master READY register

RE: SPI master READY register

Nus — Thu, 06 Nov 2014 18:35:31 GMT

finally i have found solution, READY yet needs to be written 0: after first byte transmission READY sets high, i write 0 to READY, read from RXD and write next byte to TXD. After the transmission READY sets high again.

RE: SPI master READY register

Nus — Thu, 06 Nov 2014 09:05:47 GMT

Of course, I have read refrence manual. But I can not understand how clear READY, I tried read from RXD and/or write to TXD - it takes no effect.

RE: SPI master READY register

Gilson — Tue, 04 Nov 2014 17:17:32 GMT

Since the SPI transmitter is double buffered, the second byte can be written to the TXD register immediately after the first one. The SPI master will then send these bytes in the order they are written to the TXD register. There is no need to clear the READY, you must read RXD register to clear READY.

I suggest you download nRF51_Series_Reference_manual (I got version 3.0) and check section:

26.1.3 SPI master transaction sequence

Hope this helps.