Do flash operations block DMA activity?

RE: Do flash operations block DMA activity?

Kevin Bernard — Wed, 16 Nov 2022 10:46:43 GMT

Hi,

This old thread is exactly the question I am wondering about but there is something I do not understand with the answer.

Since the CPU is stalled during flash write and erase, the CPU is not accessing any AHB slave during that time, right ? therefore I do not understand the answer to the original question.

In my project, I'm using the UARTE peripheral (with DMA) and I would like to know if during flash write/erase the UART DMA will work correctly in reception or transmission.

Best regards,

Kevin

RE: Do flash operations block DMA activity?

Jared — Fri, 08 Feb 2019 09:45:51 GMT

That is correct!

RE: Do flash operations block DMA activity?

droberson — Thu, 07 Feb 2019 15:05:35 GMT

Jey Jared,

By "slave" in this case do you mean one of the 9 AHB RAM slaves? In other words, as long as the SPIM DMA module isn't writing to the same chunk of RAM that the CPU is accessing?

Thanks,

Derek

RE: Do flash operations block DMA activity?

Jared — Thu, 07 Feb 2019 14:01:39 GMT

Hi,

Yes, this shouldn't be a problem as long as the SPI Master doesn't access the same slave as the CPU is accessing. If they did, the CPU would get the highest priority.

Best regards

Jared