<?xml version="1.0" encoding="UTF-8" ?>
<?xml-stylesheet type="text/xsl" href="https://devzone.nordicsemi.com/cfs-file/__key/system/syndication/rss.xsl" media="screen"?><rss version="2.0" xmlns:dc="http://purl.org/dc/elements/1.1/" xmlns:slash="http://purl.org/rss/1.0/modules/slash/" xmlns:wfw="http://wellformedweb.org/CommentAPI/" xmlns:atom="http://www.w3.org/2005/Atom"><channel><title>SWD causing undesirable reset</title><link>https://devzone.nordicsemi.com/f/nordic-q-a/4362/swd-causing-undesirable-reset</link><description>Hello 
 I have an nRF51822 serving as s supervisory micro for an embedded Linux board. Two GPIO pins from the main CPU are hooked up to the nRF51822 to implement SWD for the purpose of upgrading the nRF. 
 I have written all the SWD code and the upgrade</description><dc:language>en-US</dc:language><generator>Telligent Community 13</generator><lastBuildDate>Thu, 12 Nov 2015 05:29:19 GMT</lastBuildDate><atom:link rel="self" type="application/rss+xml" href="https://devzone.nordicsemi.com/f/nordic-q-a/4362/swd-causing-undesirable-reset" /><item><title>RE: SWD causing undesirable reset</title><link>https://devzone.nordicsemi.com/thread/15507?ContentTypeID=1</link><pubDate>Thu, 12 Nov 2015 05:29:19 GMT</pubDate><guid isPermaLink="false">137ad170-7792-4731-bb38-c0d22fbe4515:dc94b45d-6e48-4abf-b6c0-45dc5be50f5b</guid><dc:creator>Roger Clark</dc:creator><description>&lt;p&gt;I&amp;#39;m seeing a similar problem all the time.&lt;/p&gt;
&lt;p&gt;When I have the Black Magic Probe (SWD programmer connected), it drives both SDIO and SWCK low in its initialisation sequence, however it appears that driving SDIO low causes my nRF51 to immediately reset and also Halt its operation.&lt;/p&gt;
&lt;p&gt;If I disconnect the SDIO line from the programmer and manually pull it low, it also resets and halts the processor.&lt;/p&gt;
&lt;p&gt;The work-around appears to initially drive SDIO high, as the evaluation board I&amp;#39;m using does not pull this pin high or low (i.e its floating) &lt;a href="http://www.waveshare.com/w/upload/5/57/Core51822-Schematic.pdf"&gt;www.waveshare.com/.../Core51822-Schematic.pdf&lt;/a&gt;&lt;/p&gt;
&lt;p&gt;However from what I have read, I thought that both SDIO and SWCK are supposed to be pulled low - or perhaps its just SCK that is supposed to be pulled low (as this is the configuration on my evaluation board)&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item><item><title>RE: SWD causing undesirable reset</title><link>https://devzone.nordicsemi.com/thread/15506?ContentTypeID=1</link><pubDate>Mon, 10 Nov 2014 21:07:17 GMT</pubDate><guid isPermaLink="false">137ad170-7792-4731-bb38-c0d22fbe4515:b9eff1b8-a4f4-4af8-b89d-c6d8456c4dbd</guid><dc:creator>Charles Manning</dc:creator><description>&lt;p&gt;Thanks, but there seems more to it than that. This does not appear to be deterministic.&lt;/p&gt;
&lt;p&gt;I think it would be good to clarify the documentation. The documentation seems to imply that this will not cause a reset.&lt;/p&gt;
&lt;p&gt;What seems strange to me is that I don&amp;#39;t always see it causing a reset.&lt;/p&gt;
&lt;p&gt;I have code that does this:&lt;/p&gt;
&lt;p&gt;Enter debug mode.
Fiddle some registers.
Exit debug mode (ie. enable reset)
Force a reset by holding SWDIO and  SWDCLK low for approx 10msec.
Release IO pins so that SWDIO/RESET goes high and SWDCLK stays low.&lt;/p&gt;
&lt;p&gt;If I run this program multiple times (eg. 1/second) I see the RESET during the preamble only about once per ten times.&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item><item><title>RE: SWD causing undesirable reset</title><link>https://devzone.nordicsemi.com/thread/15505?ContentTypeID=1</link><pubDate>Fri, 07 Nov 2014 10:04:30 GMT</pubDate><guid isPermaLink="false">137ad170-7792-4731-bb38-c0d22fbe4515:79043b97-84c0-4278-a74d-5171c8117c19</guid><dc:creator>Asbj&amp;#248;rn</dc:creator><description>&lt;p&gt;The first time you enter DIF a change to SWDIO line causes a reset due to the multiplexing with the nRESET functionality. So first time you enter DIF you should expect this. After that you will have to enable the reset functionality again from the RESET register.&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item></channel></rss>