SAADC Offset Calibration errors and input resistance

RE: SAADC Offset Calibration errors and input resistance

Jared — Tue, 12 Mar 2019 14:51:04 GMT

I'm suspecting that the issue might be a HW issue, more specially ground bounce on the PCB.

Could you share the schematic and layout files of the prototype?
Do you have the possibility of using differential mode and see if you're still observing the issue?

Best regards

Jared

RE: SAADC Offset Calibration errors and input resistance

while(1) — Tue, 12 Mar 2019 09:18:42 GMT

The dies are all nRF5283-QFAA-E00.

RE: SAADC Offset Calibration errors and input resistance

while(1) — Fri, 08 Mar 2019 16:23:13 GMT

Hi Jared,

Thanks for looking into this...

First i do this in my "call back"

//set the do calibration flag.
if((m_adc_evt_counter % SAADC_CALIBRATION_INTERVAL) == 0 && p_event->type == NRF_DRV_SAADC_EVT_DONE && m_saadc_calibrate_done == false ) //Evaluate if offset calibration should be performed. Configure the SAADC_CALIBRATION_INTERVAL constant to change the calibration frequency

{
nrf_drv_saadc_abort(); // Abort all ongoing conversions. Calibration cannot be run if SAADC is busy
while(NRF_SAADC->STATUS == (SAADC_STATUS_STATUS_Busy << SAADC_STATUS_STATUS_Pos))

m_saadc_calibrate = true; // Set flag to trigger calibration in main context when SAADC is stopped
}

then I do this in main

if(m_saadc_calibrate == true)
{

//Workaround
//Calibration should follow the pattern STOP -> STOPPED -> CALIBRATEOFFSET -> CALIBRATEDONE -> STOP -> STOPPED -> START.
NRF_LOG_INFO("SAADC calibration starting now... \r\n"); //
m_saadc_calibrate = false;
while(nrf_drv_saadc_calibrate_offset() != NRF_SUCCESS); //Trigger calibration task

nrf_saadc_disable();
while(NRF_SAADC->STATUS == (SAADC_STATUS_STATUS_Busy << SAADC_STATUS_STATUS_Pos))
{}
nrf_saadc_enable();
while(NRF_SAADC->STATUS == (SAADC_STATUS_STATUS_Busy << SAADC_STATUS_STATUS_Pos))
{}
m_saadc_calibrate_done = true;

}

The weird thing is the loading of our potential divider. The reading across it is way out of specification for our 0.1% resisters.

sorry for the poor formatting

also the die is nRF5283-QFAA-E00 for both examples

RE: SAADC Offset Calibration errors and input resistance

Jared — Fri, 08 Mar 2019 14:19:29 GMT

Hi,

As previously mentioned in this thread, one should have Tacq > 10 due to some Errata's. I see that you have already tried increasing it, could you try: Apply STOP task after calibration, before sampling. CALIBRATEOFFSET -> CALIBRATEDONE -> STOP -> STOPPED -> START

Best regards

Jared

RE: SAADC Offset Calibration errors and input resistance

hmolesworth — Mon, 04 Mar 2019 15:51:30 GMT

There are some errata issues when Tacq < 5uSecs, so 40uSec test rules out those. This is another errata, easy to check, which might vary between specific dies of the same code:

3.24 [86] SAADC: Triggering START task after offset calibration may write a sample to RAM

Also this one, but only for Tacq > 10uSecs

3.50 [178] SAADC: END event firing too early

Are the dies all the same code (die rev & date)? Looks like a question for Nordic team ..

RE: SAADC Offset Calibration errors and input resistance

while(1) — Mon, 04 Mar 2019 09:18:20 GMT

Hi hmolesworth,

Thanks for taking your time to look at this. I have the same results with 40uS with no change or improvements. We have also swapped all the external components from one board to the other. My issue here is two distinct difference in operation from one device to another, both with the same firmware and operating conditions. It's my hunch that what ever is loading our external p.d. is also affecting the calibration.

RE: SAADC Offset Calibration errors and input resistance

hmolesworth — Fri, 01 Mar 2019 16:36:40 GMT

As a test you might try slowing down the sampling (say to 10uSec) just in case those parts have higher external impedance for some reason, maybe component tolerance or even incorrect components in the case of resistors or damaged if there are any aliasing filter capacitors. The calibration is ineffective if the sampling time doesn't allow full 12-bit settle on the internal sampling capacitor.

TACQ [μs]    Max source resistance [kOhm]
      3               10
      5               40
      10             100
      15             200
      20             400
      40             800