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<?xml-stylesheet type="text/xsl" href="https://devzone.nordicsemi.com/cfs-file/__key/system/syndication/rss.xsl" media="screen"?><rss version="2.0" xmlns:dc="http://purl.org/dc/elements/1.1/" xmlns:slash="http://purl.org/rss/1.0/modules/slash/" xmlns:wfw="http://wellformedweb.org/CommentAPI/" xmlns:atom="http://www.w3.org/2005/Atom"><channel><title>Toggle gpio certain number of times with PPI</title><link>https://devzone.nordicsemi.com/f/nordic-q-a/44889/toggle-gpio-certain-number-of-times-with-ppi</link><description>Using nRF5_SDK_15.3.0, soft device 132 (Rigado BMD-300 eval kit), segger embedded studio 
 
 I&amp;#39;m trying to control ADS1231 by listening for DRDY to go low and pulse an output to SCLK 25 times (shift 24bits and one more to get the data line to go high</description><dc:language>en-US</dc:language><generator>Telligent Community 13</generator><lastBuildDate>Thu, 28 Mar 2019 14:08:31 GMT</lastBuildDate><atom:link rel="self" type="application/rss+xml" href="https://devzone.nordicsemi.com/f/nordic-q-a/44889/toggle-gpio-certain-number-of-times-with-ppi" /><item><title>RE: Toggle gpio certain number of times with PPI</title><link>https://devzone.nordicsemi.com/thread/178968?ContentTypeID=1</link><pubDate>Thu, 28 Mar 2019 14:08:31 GMT</pubDate><guid isPermaLink="false">137ad170-7792-4731-bb38-c0d22fbe4515:0ea77ae0-010b-4cc5-85f7-ea20d8f56d0c</guid><dc:creator>grantka</dc:creator><description>&lt;p&gt;This is what I ended up doing, except I took out PPI entirely.&amp;nbsp; My /DRDY event interrupt disables the event and kicks off the SPI transfer, then the SPI completion interrupt re-enables the GPIOTE event.&amp;nbsp; Very simple and works well.&amp;nbsp;&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item><item><title>RE: Toggle gpio certain number of times with PPI</title><link>https://devzone.nordicsemi.com/thread/178778?ContentTypeID=1</link><pubDate>Wed, 27 Mar 2019 17:24:29 GMT</pubDate><guid isPermaLink="false">137ad170-7792-4731-bb38-c0d22fbe4515:fc387c39-b650-4eb8-afdb-118319abbe65</guid><dc:creator>hmolesworth</dc:creator><description>&lt;p&gt;I see the issue; that would imply using the /DRDY event to start a hardware timer which would provide a delay long enough to ensure the interrupt would execute before that timer would trigger the SPI transfer via a PPI compare event. Alternatively and simpler since the update rate is so slow - 10 or 80 times per second - the event interrupt could simply set a flag which the wakeup in main() following this interrupt would check and use to first disable the PPI and restore the /DRDY and then manually start the SPI transfer. The SPI completion interrupt would then revert the /DRDY back to PPI wakeup.&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item><item><title>RE: Toggle gpio certain number of times with PPI</title><link>https://devzone.nordicsemi.com/thread/178767?ContentTypeID=1</link><pubDate>Wed, 27 Mar 2019 16:32:27 GMT</pubDate><guid isPermaLink="false">137ad170-7792-4731-bb38-c0d22fbe4515:40af4439-710b-4ff5-9164-5308928fd7db</guid><dc:creator>grantka</dc:creator><description>&lt;p&gt;I had to change this to not be the answer.&amp;nbsp; I cannot seem to get this solution working reliably.&amp;nbsp; As far as I know, there is no way to disable the ppi channel after the /DRDY event is triggered to prevent it from re-firing besides using the gpiote event callback.&amp;nbsp; Unfortunately, the timing is such that every once in a while the PPI event fires twice before the irq can disable it, resulting in erroneous reads.&amp;nbsp;&lt;/p&gt;
&lt;p&gt;I proved to myself that this is the cause by injecting a delay in the irq before&amp;nbsp; calling nrfx_gpiote_in_event_disable and noted that the probability of misreads went up as more delay was injected, and it only took 10us to misread every time.&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item><item><title>RE: Toggle gpio certain number of times with PPI</title><link>https://devzone.nordicsemi.com/thread/177425?ContentTypeID=1</link><pubDate>Wed, 20 Mar 2019 15:57:44 GMT</pubDate><guid isPermaLink="false">137ad170-7792-4731-bb38-c0d22fbe4515:7366e347-4daa-40f3-bb3e-043cb8ae2c02</guid><dc:creator>grantka</dc:creator><description>&lt;p&gt;thanks for the response!&amp;nbsp; I&amp;#39;m trying to implement this now but not sure how to appropriately change /DRDY back to SPI MISO function.&amp;nbsp;&lt;/p&gt;
&lt;p&gt;I have a GPIOTE event when /DRDY transitions HITOLO, and I have that hooked up to PPI to start the SPI transfer.&amp;nbsp;&lt;/p&gt;
&lt;p&gt;Can I use the GPIOTE interrupt to disable GPIOTE on /DRDY while the SPI transfer takes place?&amp;nbsp; Or will that interfere with how PPI receives the event?&amp;nbsp;&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item><item><title>RE: Toggle gpio certain number of times with PPI</title><link>https://devzone.nordicsemi.com/thread/176504?ContentTypeID=1</link><pubDate>Fri, 15 Mar 2019 16:50:02 GMT</pubDate><guid isPermaLink="false">137ad170-7792-4731-bb38-c0d22fbe4515:15b87c1c-d971-4eb2-b5d8-22c804743d21</guid><dc:creator>hmolesworth</dc:creator><description>&lt;p&gt;You might try SPI; you would still have to use /DRDY as the trigger by changing the pin to the input sense and then changing it back to the SPI MISO function. Unless you require to poll /DRDY at other places in the code then the 25th clock is superfluous; just use 3-byte 24-bit transfer then revert /DRDY to wait for the next transition. The change from the L or H state - depending on last data bit - would be handled by the AFE when it generates the next falling edge, as it automatically pusghes /DRDY high before issuing falling edge.&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item></channel></rss>