RE: QSPI clock cycles shifted

Adam Gerken — Fri, 12 Apr 2019 14:21:07 GMT

Yeah, that totally worked. Thank you! I don't think I would have figured that out. Just for my own education, why isn't the qspi example like that?

RE: QSPI clock cycles shifted

Stian Røed Hafskjold — Fri, 12 Apr 2019 11:31:22 GMT

I think I know what the problem is. The m_buffer_tx[4] variable you have is not word aligned. Since it's an array of bytes (uint8_t not uint32_t), you are not guaranteed that it will be word aligned in RAM. The QSPI peripheral READ and WRITE SRC registers have to point to a word aligned address, i.e. ending with 0x0, 0x4, 0x08, 0xC. https://infocenter.nordicsemi.com/topic/ps_nrf52840/qspi.html?cp=3_0_0_5_18_9_14#register.WRITE.SRC

Try to add __ALIGN(4) in front of the variable declaration and see if that helps.

__ALIGN(4) static uint8_t m_buffer_tx[4] = {0xDE,0xAD,0xBE,0xEF};

RE: QSPI clock cycles shifted

Adam Gerken — Thu, 11 Apr 2019 18:15:04 GMT

Yes, I agree the QSPI example works just fine. That's also what I followed, which is why I'm so confused!

Here is my initialization code:

static void qspi_init(void){

    uint8_t temporary = 0x40;
    uint32_t err_code;

    //Init the perif
    nrfx_qspi_config_t config = NRFX_QSPI_DEFAULT_CONFIG;

    err_code = nrfx_qspi_init(&config, qspi_handler, NULL);
    APP_ERROR_CHECK(err_code);

    //configure the Flash
    nrf_qspi_cinstr_conf_t cinstr_cfg = {
        .opcode    = QSPI_STD_CMD_RSTEN,
        .length    = NRF_QSPI_CINSTR_LEN_1B,
        .io2_level = true,
        .io3_level = true,
        .wipwait   = true,
        .wren      = true
    };

    // Send reset enable
    err_code = nrfx_qspi_cinstr_xfer(&cinstr_cfg, NULL, NULL);
    APP_ERROR_CHECK(err_code);

    // Send reset command
    cinstr_cfg.opcode = QSPI_STD_CMD_RST;
    err_code = nrfx_qspi_cinstr_xfer(&cinstr_cfg, NULL, NULL);
    APP_ERROR_CHECK(err_code);

    // Switch to qspi mode
    cinstr_cfg.opcode = QSPI_STD_CMD_WRSR;
    cinstr_cfg.length = NRF_QSPI_CINSTR_LEN_2B;
    err_code = nrfx_qspi_cinstr_xfer(&cinstr_cfg, &temporary, NULL);
    APP_ERROR_CHECK(err_code);

    //Test the Flash by checking the device and mfg ids
    static uint8_t temp_rx_buf[5];
    static uint8_t temp_tx_buf[] = {0,0,0,0,0};

    cinstr_cfg.opcode = QSPI_STD_CMD_MFG_DEV_ID;
    cinstr_cfg.length = NRF_QSPI_CINSTR_LEN_6B;
    cinstr_cfg.wren   = false;

    nrfx_qspi_cinstr_xfer(&cinstr_cfg, temp_tx_buf, temp_rx_buf);

    printf("Flash MFG ID: 0x%X  Dev ID: 0x%X\r\n", temp_rx_buf[3], temp_rx_buf[4]);

    if((temp_rx_buf[3] != MFG_ID)||(temp_rx_buf[4] != DEVICE_ID)){
      printf("Hardware Error: FLASH INCORRECT\r\n");
      while(1);
    }

    printf("qspi_init\r\n");

}

This seems to work fine, I get the correct Device ID from the Flash, and all the registers seems to get set up correctly.

My event handler:

static void qspi_handler(nrfx_qspi_evt_t event, void * p_context)
{
    UNUSED_PARAMETER(event);
    UNUSED_PARAMETER(p_context);
    m_qspi_finished = true;
}

Also seems to work just fine.

I call my qspi_init routine, then go into my main loop:

  while(1){

    uint8_t err_code;
    static uint8_t m_buffer_tx[4] = {0xDE,0xAD,0xBE,0xEF};
    static uint8_t m_buffer_rx[4];

    err_code = nrfx_qspi_write(m_buffer_tx, 4, 0);
    APP_ERROR_CHECK(err_code);
    while(!m_qspi_finished);
    m_qspi_finished = false;

    err_code = nrfx_qspi_read(m_buffer_rx, 4, 0);
    APP_ERROR_CHECK(err_code);
    while(!m_qspi_finished);
    m_qspi_finished = false;

    printf("Why did the cow cross the road: %X%X%X%X\r", m_buffer_rx[3],m_buffer_rx[2],m_buffer_rx[1],m_buffer_rx[0]);
    nrf_delay_ms(100);

  }//main while loop

This is where I see the above analyzer traces. The read function seems to return garbage most of the time.

Here is the QSPI portion of my sdk_config:

// <e> NRFX_QSPI_ENABLED - nrfx_qspi - QSPI peripheral driver
//==========================================================
#ifndef NRFX_QSPI_ENABLED
#define NRFX_QSPI_ENABLED 1
#endif
// <o> NRFX_QSPI_CONFIG_SCK_DELAY - tSHSL, tWHSL and tSHWL in number of 16 MHz periods (62.5 ns).  <0-255> 


#ifndef NRFX_QSPI_CONFIG_SCK_DELAY
#define NRFX_QSPI_CONFIG_SCK_DELAY 1
#endif

// <o> NRFX_QSPI_CONFIG_XIP_OFFSET - Address offset in the external memory for Execute in Place operation. 
#ifndef NRFX_QSPI_CONFIG_XIP_OFFSET
#define NRFX_QSPI_CONFIG_XIP_OFFSET 0
#endif

// <o> NRFX_QSPI_CONFIG_READOC  - Number of data lines and opcode used for reading.
 
// <0=> FastRead 
// <1=> Read2O 
// <2=> Read2IO 
// <3=> Read4O 
// <4=> Read4IO 

#ifndef NRFX_QSPI_CONFIG_READOC
#define NRFX_QSPI_CONFIG_READOC 0
#endif

// <o> NRFX_QSPI_CONFIG_WRITEOC  - Number of data lines and opcode used for writing.
 
// <0=> PP 
// <1=> PP2O 
// <2=> PP4O 
// <3=> PP4IO 

#ifndef NRFX_QSPI_CONFIG_WRITEOC
#define NRFX_QSPI_CONFIG_WRITEOC 0
#endif

// <o> NRFX_QSPI_CONFIG_ADDRMODE  - Addressing mode.
 
// <0=> 24bit 
// <1=> 32bit 

#ifndef NRFX_QSPI_CONFIG_ADDRMODE
#define NRFX_QSPI_CONFIG_ADDRMODE 0
#endif

// <o> NRFX_QSPI_CONFIG_MODE  - SPI mode.
 
// <0=> Mode 0 
// <1=> Mode 1 

#ifndef NRFX_QSPI_CONFIG_MODE
#define NRFX_QSPI_CONFIG_MODE 0
#endif

// <o> NRFX_QSPI_CONFIG_FREQUENCY  - Frequency divider.
 
// <0=> 32MHz/1 
// <1=> 32MHz/2 
// <2=> 32MHz/3 
// <3=> 32MHz/4 
// <4=> 32MHz/5 
// <5=> 32MHz/6 
// <6=> 32MHz/7 
// <7=> 32MHz/8 
// <8=> 32MHz/9 
// <9=> 32MHz/10 
// <10=> 32MHz/11 
// <11=> 32MHz/12 
// <12=> 32MHz/13 
// <13=> 32MHz/14 
// <14=> 32MHz/15 
// <15=> 32MHz/16 

#ifndef NRFX_QSPI_CONFIG_FREQUENCY
#define NRFX_QSPI_CONFIG_FREQUENCY 15
#endif

// <s> NRFX_QSPI_PIN_SCK - SCK pin value.
#ifndef NRFX_QSPI_PIN_SCK
#define NRFX_QSPI_PIN_SCK 19
#endif

// <s> NRFX_QSPI_PIN_CSN - CSN pin value.
#ifndef NRFX_QSPI_PIN_CSN
#define NRFX_QSPI_PIN_CSN 17
#endif

// <s> NRFX_QSPI_PIN_IO0 - IO0 pin value.
#ifndef NRFX_QSPI_PIN_IO0
#define NRFX_QSPI_PIN_IO0 20
#endif

// <s> NRFX_QSPI_PIN_IO1 - IO1 pin value.
#ifndef NRFX_QSPI_PIN_IO1
#define NRFX_QSPI_PIN_IO1 21
#endif

// <s> NRFX_QSPI_PIN_IO2 - IO2 pin value.
#ifndef NRFX_QSPI_PIN_IO2
#define NRFX_QSPI_PIN_IO2 22
#endif

// <s> NRFX_QSPI_PIN_IO3 - IO3 pin value.
#ifndef NRFX_QSPI_PIN_IO3
#define NRFX_QSPI_PIN_IO3 23
#endif

// <o> NRFX_QSPI_CONFIG_IRQ_PRIORITY  - Interrupt priority
 
// <0=> 0 (highest) 
// <1=> 1 
// <2=> 2 
// <3=> 3 
// <4=> 4 
// <5=> 5 
// <6=> 6 
// <7=> 7 

#ifndef NRFX_QSPI_CONFIG_IRQ_PRIORITY
#define NRFX_QSPI_CONFIG_IRQ_PRIORITY 6
#endif

// </e>

This is SDK 15.2.0

RE: QSPI clock cycles shifted

Stian Røed Hafskjold — Thu, 11 Apr 2019 18:04:08 GMT

I tried with the QSPI SDK example and it seems to be according to spec. Can you please post the code you are using to transmit the data. Are you using the SDK drivers?

RE: QSPI clock cycles shifted

Adam Gerken — Thu, 11 Apr 2019 16:41:52 GMT

Thank you.

RE: QSPI clock cycles shifted

Stian Røed Hafskjold — Thu, 11 Apr 2019 16:25:23 GMT

Hi, sorry for not responding. I will look into it now.

RE: QSPI clock cycles shifted

Adam Gerken — Thu, 11 Apr 2019 16:08:54 GMT

Putting it in 32bit mode, seems to send 5 address bytes, with 4 sets of clock signals, followed by three data bytes. Where is this extra address/dummy byte on the data lines coming from?!

RE: QSPI clock cycles shifted

Adam Gerken — Wed, 10 Apr 2019 19:48:34 GMT

Anyone? Jørgen Holmefjord? This is driving me nuts.

Changing the number of data lines doesn't change anything:

Still sends the correct number of clocks, but sends 32 bits of zero, instead of 24 zero bits and DEADBEEF.

RE: QSPI clock cycles shifted

Adam Gerken — Tue, 09 Apr 2019 00:46:21 GMT

No ideas? No one? I still can't get this to work.