RE: nRF51 Dongle to Taiyo Yuden EBAGJNZXX eval board

Vidar Berg — Mon, 08 Apr 2019 08:09:09 GMT

Hi,

PAN #78 workaround should be implemented where you are calling nvic_systemreset/sd_nvic_systemreset in your code. E.g., in the app_error_handler and when your reset into DFU mode if you have implemented DFU support.

Yes, __SYSTEM_CLOCK must be 16, so you should revert the change you made earlier. Also, setting CLOCK_CONFIG_XTAL_FREQ to '0' is not required since UICR.XTALFREQ changes the reset value for CLOCK.XTALFREQ to 32 Mhz.

RE: nRF51 Dongle to Taiyo Yuden EBAGJNZXX eval board

william-krs — Sat, 06 Apr 2019 13:30:36 GMT

Hi Vidar,

I had addeded the UICR.XTALFREQ register update to system_nrf51.c, I also added PAN #78 code to system_nrf51.c after the UICR.XTALFREQ, is this the correct implementation of PAN #78 as it doesn't state where to put it? see below:

void SystemInit(void)
{
    /* If desired, switch off the unused RAM to lower consumption by the use of RAMON register.
       It can also be done in the application main() function. */

    /* Prepare the peripherals for use as indicated by the PAN 26 "System: Manual setup is required
       to enable the use of peripherals" found at Product Anomaly document for your device found at
       https://www.nordicsemi.com/. The side effect of executing these instructions in the devices
       that do not need it is that the new peripherals in the second generation devices (LPCOMP for
       example) will not be available. */
    // added WILLY
    if (*(uint32_t *)0x10001008 == 0xFFFFFFFF)
    {
    NRF_NVMC->CONFIG = NVMC_CONFIG_WEN_Wen << NVMC_CONFIG_WEN_Pos;
    while (NRF_NVMC->READY == NVMC_READY_READY_Busy){}
    *(uint32_t *)0x10001008 = 0xFFFFFF00;
    NRF_NVMC->CONFIG = NVMC_CONFIG_WEN_Ren << NVMC_CONFIG_WEN_Pos;
    while (NRF_NVMC->READY == NVMC_READY_READY_Busy){}
    NVIC_SystemReset();
    while (true){}
    }

    NRF_CLOCK->TASKS_HFCLKSTOP = 1;
    while (NRF_CLOCK->HFCLKSTAT & (CLOCK_HFCLKSTAT_SRC_Xtal <<
    CLOCK_HFCLKSTAT_SRC_Pos));
    NVIC_SystemReset();

    if (is_manual_peripheral_setup_needed())
    {
        *(uint32_t volatile *)0x40000504 = 0xC007FFDF;
        *(uint32_t volatile *)0x40006C18 = 0x00008000;
    }

    /* Disable PROTENSET registers under debug, as indicated by PAN 59 "MPU: Reset value of DISABLEINDEBUG
       register is incorrect" found at Product Anomaly document for your device found at
       https://www.nordicsemi.com/. There is no side effect of using these instruction if not needed. */
    if (is_disabled_in_debug_needed())
    {
        NRF_MPU->DISABLEINDEBUG = MPU_DISABLEINDEBUG_DISABLEINDEBUG_Disabled << MPU_DISABLEINDEBUG_DISABLEINDEBUG_Pos;
    }

    /* Execute the following code to eliminate excessive current in sleep mode with RAM retention in nRF51802 devices,
       as indicated by PAN 76 "System: Excessive current in sleep mode with retention" found at Product Anomaly document
       for your device found at https://www.nordicsemi.com/. */
    if (is_peripheral_domain_setup_needed()){
        if (*(uint32_t volatile *)0x4006EC00 != 1){
            *(uint32_t volatile *)0x4006EC00 = 0x9375;
            while (*(uint32_t volatile *)0x4006EC00 != 1){
            }
        }
        *(uint32_t volatile *)0x4006EC14 = 0xC0;
    }
}

Also from your comments does that mean that setting the __SYSTEM_CLOCK to 32MHz was incorrect, and that CLOCK_CONFIG_XTAL_FREQ 0 was also not required?

Thanks for your help.

RE: nRF51 Dongle to Taiyo Yuden EBAGJNZXX eval board

Vidar Berg — Fri, 05 Apr 2019 07:55:17 GMT

Hi,

The 32MHz clock signal is divided by two internally on the chip. In other words, the system clock will always be 16 MHz (__SYSTEM_CLOCK). However, for the clock source to be divided by two you need to set the non-volatile UICR.XTALFREQ register to 0x00 (see chapter 8 of the nRF51 RM).

It's also important that you implement the workaround for PAN #78 (link).

Best regards,

Vidar