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<?xml-stylesheet type="text/xsl" href="https://devzone.nordicsemi.com/cfs-file/__key/system/syndication/rss.xsl" media="screen"?><rss version="2.0" xmlns:dc="http://purl.org/dc/elements/1.1/" xmlns:slash="http://purl.org/rss/1.0/modules/slash/" xmlns:wfw="http://wellformedweb.org/CommentAPI/" xmlns:atom="http://www.w3.org/2005/Atom"><channel><title>WDT Timer Documentation Clarification</title><link>https://devzone.nordicsemi.com/f/nordic-q-a/45980/wdt-timer-documentation-clarification</link><description>From page 520 of nRF52840 Product Specification 1.0 4413_417 v1.0 / 2018-03-16 
 If the watchdog is configured to generate an interrupt on the TIMEOUT event, the watchdog reset will be postponed with two 32.768 kHz clock cycles after the TIMEOUT event</description><dc:language>en-US</dc:language><generator>Telligent Community 13</generator><lastBuildDate>Wed, 10 Apr 2019 15:52:56 GMT</lastBuildDate><atom:link rel="self" type="application/rss+xml" href="https://devzone.nordicsemi.com/f/nordic-q-a/45980/wdt-timer-documentation-clarification" /><item><title>RE: WDT Timer Documentation Clarification</title><link>https://devzone.nordicsemi.com/thread/181380?ContentTypeID=1</link><pubDate>Wed, 10 Apr 2019 15:52:56 GMT</pubDate><guid isPermaLink="false">137ad170-7792-4731-bb38-c0d22fbe4515:fde1476c-6482-4c1f-aac6-66da388b8318</guid><dc:creator>JeanMBoones</dc:creator><description>&lt;p&gt;Thanks for the clarification.&lt;/p&gt;
&lt;p&gt;-J&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item><item><title>RE: WDT Timer Documentation Clarification</title><link>https://devzone.nordicsemi.com/thread/181213?ContentTypeID=1</link><pubDate>Wed, 10 Apr 2019 06:22:23 GMT</pubDate><guid isPermaLink="false">137ad170-7792-4731-bb38-c0d22fbe4515:bac5a4f1-4002-40f3-abf8-402b27bed054</guid><dc:creator>Einar Thorsrud</dc:creator><description>&lt;p&gt;Hi,&lt;/p&gt;
&lt;p&gt;We use the &lt;a href="https://www.sciencedirect.com/topics/computer-science/clock-cycles"&gt;normal definition of &amp;quot;clock cycle&amp;quot;&lt;/a&gt;, which is the same as clock period: the time it takes for the clock signal to repeat it self. Or said differently: the time between for instance the rising edges of the clock signal. The clock period is 1/32768 = 30.5&amp;nbsp;&amp;mu;s, so you are right that two clock cycles are 61&amp;nbsp;&lt;span&gt;&amp;mu;s.&lt;/span&gt;&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item></channel></rss>