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<?xml-stylesheet type="text/xsl" href="https://devzone.nordicsemi.com/cfs-file/__key/system/syndication/rss.xsl" media="screen"?><rss version="2.0" xmlns:dc="http://purl.org/dc/elements/1.1/" xmlns:slash="http://purl.org/rss/1.0/modules/slash/" xmlns:wfw="http://wellformedweb.org/CommentAPI/" xmlns:atom="http://www.w3.org/2005/Atom"><channel><title>Configure P0.14 and P0.15 as SCL and SDA</title><link>https://devzone.nordicsemi.com/f/nordic-q-a/46110/configure-p0-14-and-p0-15-as-scl-and-sda</link><description>Hello, 
 I have a project where I&amp;#39;m using I2C. I want to configure P0.14 and P0.15 as my I2C pins as I already made a board thinking those would be available, however I get nothing on one pin and some sort of slow clock on the other (Every other pins</description><dc:language>en-US</dc:language><generator>Telligent Community 13</generator><lastBuildDate>Mon, 15 Apr 2019 08:39:08 GMT</lastBuildDate><atom:link rel="self" type="application/rss+xml" href="https://devzone.nordicsemi.com/f/nordic-q-a/46110/configure-p0-14-and-p0-15-as-scl-and-sda" /><item><title>RE: Configure P0.14 and P0.15 as SCL and SDA</title><link>https://devzone.nordicsemi.com/thread/182022?ContentTypeID=1</link><pubDate>Mon, 15 Apr 2019 08:39:08 GMT</pubDate><guid isPermaLink="false">137ad170-7792-4731-bb38-c0d22fbe4515:baf46636-a232-4ef2-bac4-ea0cdfbe3411</guid><dc:creator>Simonr</dc:creator><description>&lt;p&gt;Hi Laurent&lt;/p&gt;
&lt;p&gt;Due to the Easter holiday you will have to expect a delay in replies, sorry for the inconvenience!&lt;/p&gt;
&lt;p&gt;Normal mode can always be resumed by performing a &amp;quot;hard-reset&amp;quot; through the SWD interface:&lt;/p&gt;
&lt;ol&gt;
&lt;li&gt;Enable reset through the RESET register in the POWER peripheral.&lt;/li&gt;
&lt;li&gt;Hold the SWDCLK and SWDIO/nRESET line low for a minimum of 100 μs.&lt;/li&gt;
&lt;/ol&gt;
&lt;p&gt;Best regards,&lt;/p&gt;
&lt;p&gt;Simon&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item><item><title>RE: Configure P0.14 and P0.15 as SCL and SDA</title><link>https://devzone.nordicsemi.com/thread/181892?ContentTypeID=1</link><pubDate>Fri, 12 Apr 2019 15:35:39 GMT</pubDate><guid isPermaLink="false">137ad170-7792-4731-bb38-c0d22fbe4515:305e91ec-0908-4ada-b6e3-3a239c4cf6b5</guid><dc:creator>Laurent Bourassa</dc:creator><description>&lt;p&gt;Hi Simon,&lt;/p&gt;
&lt;p&gt;Yes, this workaround is already implemented in the project in system_nrf52.c. I tried to put it again in main.c just to make sure, but it&amp;#39;s still the same. Also, I&amp;#39;m not sure how to disable debug mode : I&amp;#39;m downloading the Release version so debug mode should be off (?).&lt;/p&gt;
&lt;p&gt;NDEBUG is defined in the solution preprocessor for Release.&lt;/p&gt;
&lt;p&gt;&lt;/p&gt;
&lt;p&gt;Laurent&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item><item><title>RE: Configure P0.14 and P0.15 as SCL and SDA</title><link>https://devzone.nordicsemi.com/thread/181826?ContentTypeID=1</link><pubDate>Fri, 12 Apr 2019 11:23:25 GMT</pubDate><guid isPermaLink="false">137ad170-7792-4731-bb38-c0d22fbe4515:d9053d92-a1a7-4ecc-98a9-d5b9d36ddc48</guid><dc:creator>Simonr</dc:creator><description>&lt;p&gt;Hi Laurent&lt;/p&gt;
&lt;p&gt;&lt;a href="https://infocenter.nordicsemi.com/index.jsp?topic=%2Ferrata_nRF52832_EngA%2FERR%2FnRF52832%2FEngineeringA%2Flatest%2Fanomaly_832_32.html&amp;amp;resultof=%22DIF%22%20%22dif%22%20"&gt;This errata&lt;/a&gt; explains that the TRACEDATA pins are automatically enabled as Trace pins when in debug mode. I am guessing this is what&amp;#39;s happening. Please check if the workaround is implemented in your project, or disable DEBUG mode.&lt;/p&gt;
&lt;p&gt;Best regards,&amp;nbsp;&lt;/p&gt;
&lt;p&gt;Simon&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item></channel></rss>