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<?xml-stylesheet type="text/xsl" href="https://devzone.nordicsemi.com/cfs-file/__key/system/syndication/rss.xsl" media="screen"?><rss version="2.0" xmlns:dc="http://purl.org/dc/elements/1.1/" xmlns:slash="http://purl.org/rss/1.0/modules/slash/" xmlns:wfw="http://wellformedweb.org/CommentAPI/" xmlns:atom="http://www.w3.org/2005/Atom"><channel><title>Setting the SCLK of my SPI master</title><link>https://devzone.nordicsemi.com/f/nordic-q-a/47810/setting-the-sclk-of-my-spi-master</link><description>Hi, 
 Sorry if my english isn&amp;#39;t perfect but I have a quick question and I could&amp;#39;t find a good answer for what I&amp;#39;m looking for. I&amp;#39;m using a FPGA Arty S7 as a SPI master and a nRF52840 as a SPI slave. I want to know if I can set my master SCLK as a value</description><dc:language>en-US</dc:language><generator>Telligent Community 13</generator><lastBuildDate>Tue, 28 May 2019 19:47:38 GMT</lastBuildDate><atom:link rel="self" type="application/rss+xml" href="https://devzone.nordicsemi.com/f/nordic-q-a/47810/setting-the-sclk-of-my-spi-master" /><item><title>RE: Setting the SCLK of my SPI master</title><link>https://devzone.nordicsemi.com/thread/189715?ContentTypeID=1</link><pubDate>Tue, 28 May 2019 19:47:38 GMT</pubDate><guid isPermaLink="false">137ad170-7792-4731-bb38-c0d22fbe4515:c72823f4-2f82-4098-b8d1-53cd60ef4b1c</guid><dc:creator>Keven</dc:creator><description>&lt;p&gt;Yeah I&amp;#39;m pretty sure I did setup everything fine (CPOL, CPHA are the same on both sides). I&amp;#39;m using the J-link RTT Viewer with the NRF_LOG_HEXDUMP_INFO function to be able to see the bytes I&amp;#39;m receiving. The oscilloscope confirms it. F&lt;span&gt;or example,&amp;nbsp;&lt;/span&gt;I&amp;#39;m receiving 4F on the first byte instead of 4E.&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item><item><title>RE: Setting the SCLK of my SPI master</title><link>https://devzone.nordicsemi.com/thread/189713?ContentTypeID=1</link><pubDate>Tue, 28 May 2019 19:24:58 GMT</pubDate><guid isPermaLink="false">137ad170-7792-4731-bb38-c0d22fbe4515:900af1bf-b43e-4e01-9a83-08df27570dc6</guid><dc:creator>awneil</dc:creator><description>[quote userid="79851" url="~/f/nordic-q-a/47810/setting-the-sclk-of-my-spi-master/189709"]the data I received was wrong[/quote]
&lt;p&gt;In what way(s) &amp;quot;wrong&amp;quot; ?&lt;/p&gt;
&lt;p&gt;Have you checked with an oscilloscope that the waveforms are all OK?&lt;/p&gt;
&lt;p&gt;Do you have the correct SPI Mode?&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item><item><title>RE: Setting the SCLK of my SPI master</title><link>https://devzone.nordicsemi.com/thread/189709?ContentTypeID=1</link><pubDate>Tue, 28 May 2019 18:13:45 GMT</pubDate><guid isPermaLink="false">137ad170-7792-4731-bb38-c0d22fbe4515:ce81e597-6664-4dbe-bc36-ccec24f83b31</guid><dc:creator>Keven</dc:creator><description>&lt;p&gt;I tried to plug in the 6.25MHz from my SPI master and the data I received was wrong. Maybe I&amp;#39;m doing something wrong and the data&amp;nbsp;should be right like you said. I&amp;#39;m going to take another look on that.&lt;/p&gt;
&lt;p&gt;Thank you for your reply.&lt;/p&gt;
&lt;p&gt;Keven&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item><item><title>RE: Setting the SCLK of my SPI master</title><link>https://devzone.nordicsemi.com/thread/189704?ContentTypeID=1</link><pubDate>Tue, 28 May 2019 16:16:49 GMT</pubDate><guid isPermaLink="false">137ad170-7792-4731-bb38-c0d22fbe4515:315eebfa-c7e4-44ec-86ca-16e8bf2867b4</guid><dc:creator>awneil</dc:creator><description>[quote userid="79851" url="~/f/nordic-q-a/47810/setting-the-sclk-of-my-spi-master"]SCLK as a value that isn&amp;#39;t in the bank&amp;nbsp;of the nRF52840 SPI (125k, 250k, ... 8mbps)[/quote]
&lt;p&gt;Surely, they only apply when the nRF is &lt;em&gt;generating&lt;/em&gt; the clock; ie, when the nRF is Master?&lt;/p&gt;
&lt;p&gt;If the nRF is the slave, then it receives its clock from the Master; it doesn&amp;#39;t have to generate it, so isn&amp;#39;t constrained by that list.&lt;/p&gt;
&lt;p&gt;The only constraint would be that you don&amp;#39;t exceed the maximum clock which the nRF can accept.&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item><item><title>RE: Setting the SCLK of my SPI master</title><link>https://devzone.nordicsemi.com/thread/189674?ContentTypeID=1</link><pubDate>Tue, 28 May 2019 13:53:47 GMT</pubDate><guid isPermaLink="false">137ad170-7792-4731-bb38-c0d22fbe4515:a2882d6e-ff89-4c2b-9375-df177aa5cada</guid><dc:creator>Keven</dc:creator><description>&lt;p&gt;The formula I&amp;#39;m using is this one :&lt;/p&gt;
&lt;p&gt;&lt;img src="https://devzone.nordicsemi.com/resized-image/__size/320x240/__key/communityserver-discussions-components-files/4/pastedimage1559051440193v1.png" alt=" " /&gt;&lt;/p&gt;
&lt;p&gt;It&amp;#39;s using the clock of my FPGA and divide it by 2 times the clk_div which make things more complicated for me. I should have put that formula in the first place&amp;nbsp;to avoid misunderstanding.&lt;/p&gt;
&lt;p&gt;Thank you for your reply,&lt;/p&gt;
&lt;p&gt;Keven&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item><item><title>RE: Setting the SCLK of my SPI master</title><link>https://devzone.nordicsemi.com/thread/189466?ContentTypeID=1</link><pubDate>Tue, 28 May 2019 07:22:15 GMT</pubDate><guid isPermaLink="false">137ad170-7792-4731-bb38-c0d22fbe4515:3f4c4321-5362-4dcc-b488-ed4ded6ade0d</guid><dc:creator>&amp;#216;yvind</dc:creator><description>&lt;p&gt;Hello Keven,&amp;nbsp;&lt;br /&gt;&lt;br /&gt;Please correct me if I&amp;#39;m wrong, but isn&amp;#39;t 100MHz/25 = 4 MHz? Are you running 50MHz? This more correct with regards to the numbers you are mentioning: 50MHz/8 = 6.25 and 50MHz/25=2MHz.&lt;br /&gt;&lt;br /&gt;Kind regards,&lt;br /&gt;Øyvind&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item></channel></rss>