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<?xml-stylesheet type="text/xsl" href="https://devzone.nordicsemi.com/cfs-file/__key/system/syndication/rss.xsl" media="screen"?><rss version="2.0" xmlns:dc="http://purl.org/dc/elements/1.1/" xmlns:slash="http://purl.org/rss/1.0/modules/slash/" xmlns:wfw="http://wellformedweb.org/CommentAPI/" xmlns:atom="http://www.w3.org/2005/Atom"><channel><title>Flashing nrf51422 through SWD interface</title><link>https://devzone.nordicsemi.com/f/nordic-q-a/5107/flashing-nrf51422-through-swd-interface</link><description>In my project, the nrf51422 chip will be hosted on a board with another CPU. I need to be able to flash the firmware through the SWD interface, controlled by the host CPU, I have already a code which is able to do it.
However, I miss one some parameters</description><dc:language>en-US</dc:language><generator>Telligent Community 13</generator><lastBuildDate>Sun, 13 Mar 2016 21:29:07 GMT</lastBuildDate><atom:link rel="self" type="application/rss+xml" href="https://devzone.nordicsemi.com/f/nordic-q-a/5107/flashing-nrf51422-through-swd-interface" /><item><title>RE: Flashing nrf51422 through SWD interface</title><link>https://devzone.nordicsemi.com/thread/17960?ContentTypeID=1</link><pubDate>Sun, 13 Mar 2016 21:29:07 GMT</pubDate><guid isPermaLink="false">137ad170-7792-4731-bb38-c0d22fbe4515:fe746355-a024-490c-84ef-30072c62e463</guid><dc:creator>harryB</dc:creator><description>&lt;p&gt;Hi There,
I am stuck at the same point where I can access the AP and DP registers of the nRF51822 but I can&amp;#39;t talk to flash. Could you please help me with the next steps? I browsed the McHck Project mentioned above but couldn&amp;#39;t find the correct information. Could you please point it to me ?&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item><item><title>RE: Flashing nrf51422 through SWD interface</title><link>https://devzone.nordicsemi.com/thread/17959?ContentTypeID=1</link><pubDate>Wed, 04 Feb 2015 10:11:24 GMT</pubDate><guid isPermaLink="false">137ad170-7792-4731-bb38-c0d22fbe4515:2f33f60b-6734-48e0-a118-6d7953b2b90d</guid><dc:creator>Vebj&amp;#248;rn</dc:creator><description>&lt;p&gt;The link applies to the nRF51xx series, yes. I was not aware of the other link you posted, good find! I am glad you were able to fix it.&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item><item><title>RE: Flashing nrf51422 through SWD interface</title><link>https://devzone.nordicsemi.com/thread/17958?ContentTypeID=1</link><pubDate>Wed, 28 Jan 2015 16:30:34 GMT</pubDate><guid isPermaLink="false">137ad170-7792-4731-bb38-c0d22fbe4515:39647c7d-4589-46a4-8f1d-e29a9a68c726</guid><dc:creator>Vito</dc:creator><description>&lt;p&gt;Your second link refers to a &amp;quot;CoreSight&lt;span class="emoticon" data-url="https://devzone.nordicsemi.com/cfs-file/__key/system/emoji/2122.svg" title="Tm"&gt;&amp;#x2122;&lt;/span&gt; PTM&lt;span class="emoticon" data-url="https://devzone.nordicsemi.com/cfs-file/__key/system/emoji/2122.svg" title="Tm"&gt;&amp;#x2122;&lt;/span&gt;-A9&amp;quot;, does it apply also to nRF51xx which are Cortex-M0?
However, I have found useful information in the source of the &lt;a href="https://github.com/mchck"&gt;McHck&lt;/a&gt; project. Following the steps in their code and partially using commands from the EFM32 posted above I programmed the flash memory succesfully.&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item><item><title>RE: Flashing nrf51422 through SWD interface</title><link>https://devzone.nordicsemi.com/thread/17955?ContentTypeID=1</link><pubDate>Wed, 28 Jan 2015 15:18:57 GMT</pubDate><guid isPermaLink="false">137ad170-7792-4731-bb38-c0d22fbe4515:951e8f3b-8e24-4cae-ab02-8fac00f70a7a</guid><dc:creator>Vebj&amp;#248;rn</dc:creator><description>&lt;p&gt;I see. The only Nordic-specific information should be listed in the manual, regarding the enter-debug-procedure. I&amp;#39;m assuming you are familiar with &lt;a href="http://www.keil.com/support/man/docs/dapdebug/dapdebug_introduction.htm"&gt;CMSIS-DAP&lt;/a&gt; in which case you can read more about the Debug Port registers here: &lt;a href="http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0401a/index.html"&gt;http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0401a/index.html&lt;/a&gt;. I will try looking into it further for a more clear answer.&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item><item><title>RE: Flashing nrf51422 through SWD interface</title><link>https://devzone.nordicsemi.com/thread/17957?ContentTypeID=1</link><pubDate>Wed, 21 Jan 2015 15:09:49 GMT</pubDate><guid isPermaLink="false">137ad170-7792-4731-bb38-c0d22fbe4515:09b6e09d-9e09-4f31-b83e-82cb2d63c4e7</guid><dc:creator>Vito</dc:creator><description>&lt;p&gt;I think you mean the equivalent of chapter 10 in rev. 2.1?
I have read that, with that I can put the CPU in debug mode. Please see my updated question, thanks!&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item><item><title>RE: Flashing nrf51422 through SWD interface</title><link>https://devzone.nordicsemi.com/thread/17956?ContentTypeID=1</link><pubDate>Wed, 21 Jan 2015 14:40:12 GMT</pubDate><guid isPermaLink="false">137ad170-7792-4731-bb38-c0d22fbe4515:42db3d16-682b-4bfd-bd1f-2ddf21269ca0</guid><dc:creator>Vebj&amp;#248;rn</dc:creator><description>&lt;p&gt;This is explained in chapter 11 in the nrf51 Reference Manual. What parameter is it that you need?&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item></channel></rss>