https://devzone.nordicsemi.com/f/nordic-q-a/51200/measuring-nrf52840-etm-trace-data-race-on-a-custom-board-busDear Nordic experts, I am trying to profile embedded S/W on a custom board (call it board #1) with a nRF52840 on it. On this board the trace pins TRACECLK and TRACEDATA[0-3] are wired to test points on the PCB. In order to connect a Segger J-Traceen-USTelligent Community 13Wed, 21 Aug 2019 12:42:58 GMThttps://devzone.nordicsemi.com/thread/205323?ContentTypeID=1Wed, 21 Aug 2019 12:42:58 GMT137ad170-7792-4731-bb38-c0d22fbe4515:d8cd7a63-621c-4434-96d7-ddba9b34e51aKenneth<p>Hi,</p> <p>Unfortunately I have not tried trace myself, but I am not aware of any specific issues other than this case:<br /><a href="https://devzone.nordicsemi.com/f/nordic-q-a/51100/traceclk-and-cpu-clock">https://devzone.nordicsemi.com/f/nordic-q-a/51100/traceclk-and-cpu-clock</a>&nbsp;</p> <p>You may consider to use SystemView by SEGGER instead.</p> <p>But to answer your questions about how to measure intersignal delay&#39;s. You should be able to set and clear all pins on a port by using:<br /><a href="https://infocenter.nordicsemi.com/topic/com.nordic.infocenter.nrf52832.ps.v1.1/gpio.html?cp=3_1_0_19_2_1#register.OUTSET">https://infocenter.nordicsemi.com/topic/com.nordic.infocenter.nrf52832.ps.v1.1/gpio.html?cp=3_1_0_19_2_1#register.OUTSET</a>&nbsp;<br /><a href="https://infocenter.nordicsemi.com/topic/com.nordic.infocenter.nrf52832.ps.v1.1/gpio.html?cp=3_1_0_19_2_2#register.OUTCLR">https://infocenter.nordicsemi.com/topic/com.nordic.infocenter.nrf52832.ps.v1.1/gpio.html?cp=3_1_0_19_2_2#register.OUTCLR</a>&nbsp;</p> <p>Any difference in timing between the signals are then caused by path delays.</p> <p>Best regards,<br />Kenneth</p><div style="clear:both;"></div>