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<?xml-stylesheet type="text/xsl" href="https://devzone.nordicsemi.com/cfs-file/__key/system/syndication/rss.xsl" media="screen"?><rss version="2.0" xmlns:dc="http://purl.org/dc/elements/1.1/" xmlns:slash="http://purl.org/rss/1.0/modules/slash/" xmlns:wfw="http://wellformedweb.org/CommentAPI/" xmlns:atom="http://www.w3.org/2005/Atom"><channel><title>SAADC end vs limit interrupt</title><link>https://devzone.nordicsemi.com/f/nordic-q-a/51262/saadc-end-vs-limit-interrupt</link><description>I was wondering: if the last sample of a buffer in the SAADC (using easyDMA and scan mode) is outside the limits, which interrupt would come first, the END or the LIMIT interrupt? Or is there no guarantee which comes first?</description><dc:language>en-US</dc:language><generator>Telligent Community 13</generator><lastBuildDate>Thu, 22 Aug 2019 12:39:37 GMT</lastBuildDate><atom:link rel="self" type="application/rss+xml" href="https://devzone.nordicsemi.com/f/nordic-q-a/51262/saadc-end-vs-limit-interrupt" /><item><title>RE: SAADC end vs limit interrupt</title><link>https://devzone.nordicsemi.com/thread/205607?ContentTypeID=1</link><pubDate>Thu, 22 Aug 2019 12:39:37 GMT</pubDate><guid isPermaLink="false">137ad170-7792-4731-bb38-c0d22fbe4515:2bc8d890-6061-4d21-8b08-5f49c21cfe65</guid><dc:creator>bart</dc:creator><description>&lt;p&gt;Cheers :)&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item><item><title>RE: SAADC end vs limit interrupt</title><link>https://devzone.nordicsemi.com/thread/205605?ContentTypeID=1</link><pubDate>Thu, 22 Aug 2019 12:34:21 GMT</pubDate><guid isPermaLink="false">137ad170-7792-4731-bb38-c0d22fbe4515:6aad2b71-32f9-45c0-91c1-beaa6383e7c4</guid><dc:creator>ovrebekk</dc:creator><description>&lt;p&gt;Hi&lt;/p&gt;
&lt;p&gt;The END event does not occur until after the sampled data is moved into RAM over the DMA. In other words this should happen after the LIMIT event, which happens as soon as the sampled data is compared to the configured limits.&amp;nbsp;&lt;/p&gt;
&lt;p&gt;The hardware designers confirmed this, and mentioned that there should be at least a 120ns delay after the LIMIT event occurs before the END event is triggered, but exactly how long it is we have not tested.&amp;nbsp;&lt;/p&gt;
&lt;p&gt;Best regards&lt;br /&gt;Torbjørn&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item></channel></rss>