Is critical section needed for glitch-less implementation of CPU sleep?

RE: Is critical section needed for glitch-less implementation of CPU sleep?

Vidar Berg — Wed, 18 Sep 2019 13:50:40 GMT

No problem, if you have masked all interrupts you need to enable SEVONPEND (ARM infocenter) to wake on pending interrupts. Otherwise, it may end up sleeping forever as you said.

RE: Is critical section needed for glitch-less implementation of CPU sleep?

Mr_BLE — Wed, 18 Sep 2019 13:34:53 GMT

Sorry for asking more deeply:

You said, the event register will be set AFTER the ISR is serviced. Does that mean, if I use the enter critical section function before calling sd_app_evt_wait() then the CPU will go to sleep and never wake up due to disabled ISR's and never setted event register?

Or is it more likely that the event register is ALWAYS set, regardles if ISR is called or not?

Thank you!

RE: Is critical section needed for glitch-less implementation of CPU sleep?

Vidar Berg — Wed, 18 Sep 2019 13:24:20 GMT

Yes, you've understood it correctly: the event register will be set after the ISR is serviced and it will become cleared by the next wfe instruction.

RE: Is critical section needed for glitch-less implementation of CPU sleep?

Mr_BLE — Wed, 18 Sep 2019 13:15:08 GMT

Thanks for answering. I understand now.

The only thing I did not know was that the event register will still be set - even after the ISR is serviced.

And the event register is only cleared by calling "__WFE()" - did I get this right?

Thank you!

RE: Is critical section needed for glitch-less implementation of CPU sleep?

Vidar Berg — Wed, 18 Sep 2019 12:57:30 GMT

I saw the ticket you linked to, but I wasn't sure what you meant by glitch-free in this context and suspected that maybe you had some other concerns than what the OP had. So to answer your question: critical regions should be redundant for this case. As pointed by the accepted answer, the event register will be set after the ISR is serviced so sd_app_evt_wait() will return immediately and reread the flag. You are thus eliminating the possibility of a race condition.

RE: Is critical section needed for glitch-less implementation of CPU sleep?

Mr_BLE — Wed, 18 Sep 2019 12:39:49 GMT

The creator of the above mentioned article showed an example code which fits exactly my needs to show an example. The creator showed a first and a second implementation of the code. Do you know what I mean, or should I copy the code in here?

RE: Is critical section needed for glitch-less implementation of CPU sleep?

Vidar Berg — Wed, 18 Sep 2019 11:58:04 GMT

Hello,

Would it be possible to include some snippets of your code here? I'm not sure I understand what you're trying to achieve in your code. E.g., Is it some code you have that has to be processed without interruption from other higher priority interrupts? Is it timing critical and/or exposed to race conditions from other application-level interrupts? Are you using a scheduler?

Thanks,

Vidar