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<?xml-stylesheet type="text/xsl" href="https://devzone.nordicsemi.com/cfs-file/__key/system/syndication/rss.xsl" media="screen"?><rss version="2.0" xmlns:dc="http://purl.org/dc/elements/1.1/" xmlns:slash="http://purl.org/rss/1.0/modules/slash/" xmlns:wfw="http://wellformedweb.org/CommentAPI/" xmlns:atom="http://www.w3.org/2005/Atom"><channel><title>SAADC Multi Channel High Current</title><link>https://devzone.nordicsemi.com/f/nordic-q-a/52381/saadc-multi-channel-high-current</link><description>Hello, 
 I have an application that requires an always running ADC to sample three channels at 4096 Hz. I have successfully adapted my application from the many examples posted by J&amp;#248;rgen, especially this one that uses the RTC to trigger ADC sample acquisition</description><dc:language>en-US</dc:language><generator>Telligent Community 13</generator><lastBuildDate>Tue, 24 Sep 2019 11:34:16 GMT</lastBuildDate><atom:link rel="self" type="application/rss+xml" href="https://devzone.nordicsemi.com/f/nordic-q-a/52381/saadc-multi-channel-high-current" /><item><title>RE: SAADC Multi Channel High Current</title><link>https://devzone.nordicsemi.com/thread/211519?ContentTypeID=1</link><pubDate>Tue, 24 Sep 2019 11:34:16 GMT</pubDate><guid isPermaLink="false">137ad170-7792-4731-bb38-c0d22fbe4515:a0c04139-c83c-46ca-87ab-49fd05adab05</guid><dc:creator>haakonsh</dc:creator><description>[quote user="nealjack"]So there is no way to disable the ADC and DMA between samples without processor intervention to get lower power? How would you architect ADC sampling to achieve the lowest current if sampling at 4kHz?[/quote]
&lt;p&gt;If you do not need to have the BLE stack running at the same time as you&amp;#39;re sampling you can sample the SAADC &amp;quot;manually&amp;quot; by enabling and disabling the SAADC between each sampling event and only take one sample.&amp;nbsp;This will remove the base ~1.1mA EasyDMA current,&amp;nbsp;at the cost of having to wake up the CPU at precise timings intervals. It might reduce the current consumption by a fair bit.&amp;nbsp;&lt;br /&gt;&lt;br /&gt;How do you&amp;nbsp;process the samples btw?&amp;nbsp;&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item><item><title>RE: SAADC Multi Channel High Current</title><link>https://devzone.nordicsemi.com/thread/211376?ContentTypeID=1</link><pubDate>Mon, 23 Sep 2019 18:06:23 GMT</pubDate><guid isPermaLink="false">137ad170-7792-4731-bb38-c0d22fbe4515:6042066b-0f31-44f9-9c66-37a3ea27f8c7</guid><dc:creator>nealjack</dc:creator><description>&lt;p&gt;So there is no way to disable the ADC and DMA between samples without processor intervention to get lower power? How would you architect ADC sampling to achieve the lowest current if sampling at 4kHz?&lt;/p&gt;
&lt;p&gt;As far as I can tell, my processor is sleeping almost the entire second except for when the ADC generates an interrupt indicating sampling is finished, so I&amp;#39;m not quite sure I buy that 500-600uA is from CPU. I can create a time-series measurement of current in the next few days to verify this.&lt;/p&gt;
&lt;p&gt;&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item><item><title>RE: SAADC Multi Channel High Current</title><link>https://devzone.nordicsemi.com/thread/211341?ContentTypeID=1</link><pubDate>Mon, 23 Sep 2019 15:00:19 GMT</pubDate><guid isPermaLink="false">137ad170-7792-4731-bb38-c0d22fbe4515:31745fb9-9001-4b70-86f7-b9f74e7b330f</guid><dc:creator>haakonsh</dc:creator><description>&lt;p&gt;The SAADC operation&amp;nbsp;is specced at ~1.24mA in&amp;nbsp;&lt;a title="SAADC active" href="https://infocenter.nordicsemi.com/topic/ps_nrf52840/_tmp/graviton/autodita/CURRENT/parameters.i_saadc.html?cp=3_0_0_4_1_0_6"&gt;SAADC active&lt;/a&gt;&amp;nbsp;(at 16kHz, at 3V, with DCDC), so you should expect around that for 4kHz as well.&amp;nbsp;&lt;br /&gt;&lt;br /&gt;I think the last ~500-600µA is CPU activity.&amp;nbsp;&lt;br /&gt;&lt;br /&gt;A current consumption scope is actually very useful in this scenario, as it should tell you how much time the CPU is active during this period.&amp;nbsp;&lt;br /&gt;&lt;br /&gt;Your RTC sampling timer is right on the money btw.&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item><item><title>RE: SAADC Multi Channel High Current</title><link>https://devzone.nordicsemi.com/thread/211023?ContentTypeID=1</link><pubDate>Fri, 20 Sep 2019 20:09:18 GMT</pubDate><guid isPermaLink="false">137ad170-7792-4731-bb38-c0d22fbe4515:dfe730bc-5a1b-45f5-88ec-a7b806f5b092</guid><dc:creator>nealjack</dc:creator><description>&lt;p&gt;So I think I figured it out. I returned to my PPI implementation, and increased the buffer size to 3 (channels) * 4096 (samples). I kept my RTC configuration the same because I still want to sample at 4096 samples per second. I know get an interrupt every second with a full buffer of data that looks correct. I&amp;#39;m measuring 1.8mA still. Is this the lower bound I can expect for 3 channels @ 4096Hz?&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item><item><title>RE: SAADC Multi Channel High Current</title><link>https://devzone.nordicsemi.com/thread/211022?ContentTypeID=1</link><pubDate>Fri, 20 Sep 2019 19:48:32 GMT</pubDate><guid isPermaLink="false">137ad170-7792-4731-bb38-c0d22fbe4515:4f337dff-e806-44cd-b247-bfbcb167d741</guid><dc:creator>nealjack</dc:creator><description>&lt;p&gt;Hi haakonsh, thanks for the answer!&lt;/p&gt;
&lt;p&gt;If I&amp;#39;m understanding this correctly, DMA and interrupts waking up the core are the primary contributors to current draw. DMA will be required regardless of buffer size and the number of samples the ADC collects before generating an interrupt. You&amp;#39;re right that reducing the number of times the core is woken up will significantly reduce current draw. This is the next thing I want to try.&lt;/p&gt;
&lt;p&gt;For my application, I want to run the ADC at 4096 samples per second, and I&amp;#39;m fine with processing these samples every second. I am fine using double buffers of size 4096. I am unsure how to get the ADC to sample at this rate, however. I see that it has an internal clock that can drive a continuous sample capture, but this functionality is not exposed by the SAADC driver. Can you point me to the right resources to achieve this?&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item><item><title>RE: SAADC Multi Channel High Current</title><link>https://devzone.nordicsemi.com/thread/210850?ContentTypeID=1</link><pubDate>Fri, 20 Sep 2019 08:05:27 GMT</pubDate><guid isPermaLink="false">137ad170-7792-4731-bb38-c0d22fbe4515:4fda24d1-b32f-4219-977a-7e6a0e5fbd95</guid><dc:creator>haakonsh</dc:creator><description>&lt;p&gt;It&amp;#39;s Actually EasyDMA that&amp;#39;s causing most of the SAADC&amp;#39;s run current of ~1.24mA (~1.1mA is DMA), what you&amp;#39;re seeing&amp;nbsp;above that is most likely increased CPU activity.&amp;nbsp;&lt;br /&gt;&amp;nbsp;&lt;br /&gt;With &amp;#39;#define SAADC_SAMPLES_IN_BUFFER 3&amp;#39;, and three channels enabled you will only get one sample per channel before the END event is fired, where you process the data and the driver initializes the buffer again. This causes a significant overhead at 16kHz, and there&amp;#39;s zero chance the&amp;nbsp;&lt;a href="https://www.st.com/resource/en/datasheet/stm32l4r5zi.pdf"&gt;STM32L4&lt;/a&gt;&amp;nbsp;is anywhere near it&amp;#39;s&amp;nbsp;ADC&amp;#39;s&amp;nbsp;run current in that scenario.&amp;nbsp;With a similar µA/Hz CPU, that overhead is just as big for that device, and they don&amp;#39;t seem to specify the run current of their DMA controller.&amp;nbsp;&lt;br /&gt;&lt;br /&gt;You need to increase the buffer size as much as you can in order to reduce the CPU overhead. What latency requirements do you have for processing your samples?&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item></channel></rss>