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<?xml-stylesheet type="text/xsl" href="https://devzone.nordicsemi.com/cfs-file/__key/system/syndication/rss.xsl" media="screen"?><rss version="2.0" xmlns:dc="http://purl.org/dc/elements/1.1/" xmlns:slash="http://purl.org/rss/1.0/modules/slash/" xmlns:wfw="http://wellformedweb.org/CommentAPI/" xmlns:atom="http://www.w3.org/2005/Atom"><channel><title>NRF52 PWM Sequence idle State</title><link>https://devzone.nordicsemi.com/f/nordic-q-a/52780/nrf52-pwm-sequence-idle-state</link><description>Hello, 
 i&amp;#39;am trying to control the pwm Idle State Level. 
 
 between my Sequence&amp;#39;s (1sek) the PIN stays High But i need it low. 
 I try to set the GPIO Out Register, but this didn&amp;#39;t work. 
 
 uint32_t seq0_ram[9]= {0x80198019,0x80108010,0x80198019,0x80148014</description><dc:language>en-US</dc:language><generator>Telligent Community 13</generator><lastBuildDate>Mon, 07 Oct 2019 06:59:25 GMT</lastBuildDate><atom:link rel="self" type="application/rss+xml" href="https://devzone.nordicsemi.com/f/nordic-q-a/52780/nrf52-pwm-sequence-idle-state" /><item><title>RE: NRF52 PWM Sequence idle State</title><link>https://devzone.nordicsemi.com/thread/213543?ContentTypeID=1</link><pubDate>Mon, 07 Oct 2019 06:59:25 GMT</pubDate><guid isPermaLink="false">137ad170-7792-4731-bb38-c0d22fbe4515:e7daca48-9c97-4066-aac7-520647006337</guid><dc:creator>elangel</dc:creator><description>&lt;p&gt;Thank you so much.&lt;/p&gt;
&lt;p&gt;i tried so much in the sequence. I had to add 0xFF because, without 0xFF the sequence didn&amp;#39;t stop. But i didn&amp;#39;t try to add a 0x8000 for the last 16 bit.&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item><item><title>RE: NRF52 PWM Sequence idle State</title><link>https://devzone.nordicsemi.com/thread/213541?ContentTypeID=1</link><pubDate>Mon, 07 Oct 2019 06:45:45 GMT</pubDate><guid isPermaLink="false">137ad170-7792-4731-bb38-c0d22fbe4515:ceec67e9-5398-433a-a30d-8cb46c890e08</guid><dc:creator>elangel</dc:creator><description>&lt;p&gt;yes, i know.&lt;/p&gt;
&lt;p&gt;&lt;/p&gt;
&lt;p&gt;But that just change the polarity in the sequence. between the sequences its still HIGH.&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item><item><title>RE: NRF52 PWM Sequence idle State</title><link>https://devzone.nordicsemi.com/thread/213080?ContentTypeID=1</link><pubDate>Thu, 03 Oct 2019 01:03:24 GMT</pubDate><guid isPermaLink="false">137ad170-7792-4731-bb38-c0d22fbe4515:108645bf-5cf3-49ee-a53e-b094377b9959</guid><dc:creator>hmolesworth</dc:creator><description>&lt;p&gt;Edit:&amp;nbsp;The last 16-bit value in the DMA table is 0x0000 (ie 0xFF 32-bit, which is interpreted as 0x00FF followed by 0x0000). In the code above that leaves the port pin high. As Sigurd suggests, change the 0xFF to 0x800000FF which leaves the last 16-bit value 0x8000 and the port pin low.&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item><item><title>RE: NRF52 PWM Sequence idle State</title><link>https://devzone.nordicsemi.com/thread/213056?ContentTypeID=1</link><pubDate>Wed, 02 Oct 2019 16:22:03 GMT</pubDate><guid isPermaLink="false">137ad170-7792-4731-bb38-c0d22fbe4515:e3b840dc-4f10-4854-a569-00af9d8838fb</guid><dc:creator>Sigurd</dc:creator><description>&lt;p&gt;Hi,&lt;/p&gt;
&lt;p&gt;&lt;span&gt;The the most significant bit[15] in the sequence (seq0_ram)&amp;nbsp;sets the polarity. See &lt;a href="https://infocenter.nordicsemi.com/topic/com.nordic.infocenter.nrf52832.ps.v1.1/pwm.html?cp=3_1_0_46_1#concept_wxj_hnw_nr"&gt;this &lt;/a&gt;and &lt;a href="https://devzone.nordicsemi.com/f/nordic-q-a/12490/nrf52-pwm-up-down-counter-mode#post-id-71632"&gt;this &lt;/a&gt;link.&lt;/span&gt;&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item></channel></rss>