SPIS data shift on first transferhttps://devzone.nordicsemi.com/f/nordic-q-a/55196/spis-data-shift-on-first-transferHello, I have two micro-controllers communicating over SPI. The STM32F746 is SPI master. The nRF52840 is SPI slave. I use SDK v15.3. I am sending two bytes over SPI from the STM32F746 to the nRF52840 every 5-30 milliseconds. The MISO data of theen-USTelligent Community 13Wed, 04 Dec 2019 09:48:45 GMTRE: SPIS data shift on first transferhttps://devzone.nordicsemi.com/thread/223527?ContentTypeID=1Wed, 04 Dec 2019 09:48:45 GMT137ad170-7792-4731-bb38-c0d22fbe4515:33b813bf-186c-47e9-96f5-53405e6f6be5YBR<p>I&#39;ve actually found the problem.</p> <p>The SPIS module on the nRF52840 was ready before the SPI Master on the STM32F746.</p> <p>The SPIS module must have &quot;registered&quot; something while lines were not yet stable. With an extra GPIO &quot;ready&quot;, it is possible to postpone the configuration of the SPIS module to after the lines have been stabilized.</p><div style="clear:both;"></div>RE: SPIS data shift on first transferhttps://devzone.nordicsemi.com/thread/223504?ContentTypeID=1Wed, 04 Dec 2019 09:10:46 GMT137ad170-7792-4731-bb38-c0d22fbe4515:7453d9e3-4340-43a8-b8e6-007efed83192Kenneth<p>Do you have any logic analyzer trace to share? A 1-bit shift seems very much like an mismatch issue with the mode/polarity of SPI, so you may want to change mode/polarity to see what impact that has one the 1-bit shift.</p> <p>Kenneth</p><div style="clear:both;"></div>