A strange question about qspi

RE: A strange question about qspi

outspace — Fri, 20 Dec 2019 13:54:55 GMT

ok,thank you very much.

RE: A strange question about qspi

Kenneth — Tue, 17 Dec 2019 19:46:06 GMT

[quote user="outspace"]The qspi peripheral will automatically control the DIR_OVERRIDE control output direction,and INPUT_OVERRIDE also controls the connection of INPUT to the input buffer, right?[/quote]

Yes. This is fully handled in hardware by the peripheral automatically when enabled.

Best regards,
Kenneth

RE: A strange question about qspi

outspace — Tue, 17 Dec 2019 04:32:01 GMT

Thank you very much for your professional answer,In response to the above question 2:

The qspi peripheral will automatically control the DIR_OVERRIDE control output direction,and INPUT_OVERRIDE also controls the connection of INPUT to the input buffer, right?Is the qspi write the red line 1 in the picture, and the read is the blue line 2 in the picture?

RE: A strange question about qspi

Kenneth — Mon, 16 Dec 2019 15:27:51 GMT

If you set the PSEL registers of a peripheral and enable the peripheral, then it is the peripheral that control those PSEL pins. You still may consider using nrf_gpio to have control over the drive strength and/or if you want to enable pull up/down on the pins, also you can set at the same time the disconnect/input/output state of the pins should fall back to when disable the peripheral. In other words it is a good idea to call nrf_gpio to set the PSEL pins to the state they should be in when the peripheral is both enabled and disabled (inactive). Pull up/down if enabled is approx 13kohm.

RE: A strange question about qspi

outspace — Mon, 16 Dec 2019 14:23:57 GMT

Hi，Kenneth

Thank you very much for your answer. I want to trouble you a little bit more. Can you answer the questions I, 2, 3, 4 specifically asked?

RE: A strange question about qspi

Kenneth — Mon, 16 Dec 2019 14:16:46 GMT

Hi,

I expect that gpio standard drive strength is not sufficient here to meet 32MHz fall and rise times, so you can't use S0S1, but need to use H0H1 (high drive) when configure qspi pins.

Best regards,
Kenneth