Peripheral interrupt setting with S112

RE: Peripheral interrupt setting with S112

yf13 — Tue, 14 Jan 2020 01:33:10 GMT

Thanks for the highlights. Now I can see that the maximum delay is within 250us, as shown in the tISR(0),PostProcessing row.

I will close this ticket.

RE: Peripheral interrupt setting with S112

Vidar Berg — Mon, 13 Jan 2020 07:45:45 GMT

[quote user="yf13"]Though I can't get clear info about the maximum IRQ delays caused by s112,[/quote]

ISR (priority 0) processing times are specified for given Softdevice events: Bluetooth Low Energy processor usage patterns

RE: Peripheral interrupt setting with S112

yf13 — Sat, 11 Jan 2020 05:14:26 GMT

Though I can't get clear info about the maximum IRQ delays caused by s112, so far with slower sampling rate everything looks fine. I would like to put this ticket to monitoring status but don't know how yet.

RE: Peripheral interrupt setting with S112

yf13 — Wed, 01 Jan 2020 00:26:57 GMT

To avoid interrupt CPU too much, I am using repeated SPIM with array list and use a counter to counter SPIM END events and then interrupt CPU.

According to your description, I probably need another counter B for the STARTED events and in the IRQ handler B to setup the new xfer registers? won't the IRQ B gets delayed by higher priority interrupts of s112 for more than 60us?

RE: Peripheral interrupt setting with S112

Turbo J — Tue, 31 Dec 2019 19:07:03 GMT

You can setup the easydma stuff in advance as the registers are double buffered.

The caveat is you need to wait for the STARTED event.

It it propably a good idea to handle this event in the SPIM interrupt and put the new DMA buffers in those TXD.PTR and RXD.PTR registers.

This way the only thing that requires 60µs timing is the actual PPI event itself.

RE: Peripheral interrupt setting with S112

yf13 — Mon, 30 Dec 2019 23:37:17 GMT

I have been using PPI to control the data collection in batches. The problem is that when the SPIM list buffer is full, the COMPARE interrupt happens and my IRQ is called. Within the IRQ, I must setup new SPIM list within 60us otherwise I am afraid the new data will cause old list to grow beyond allowed buffer. So offloading data collection to PPI doesn't solve the IRQ delay issue.

If 60us is too tight for s112, how about 120us?

RE: Peripheral interrupt setting with S112

Turbo J — Mon, 30 Dec 2019 12:02:59 GMT

Setup the SPIM transaction beforehand, use a PPI channel to actually start it (triggered via GPIOTE).

RE: Peripheral interrupt setting with S112

Vidar Berg — Mon, 30 Dec 2019 09:35:12 GMT

The 60us timing requirement will not be guaranteed with the Softdevice enabled, unfortunately. However, I think you should be able to reduce this requirement significantly by changing the way you use the SPIM. You can, for instance, connect the TIMER COMPARE event directly to the SPIM start task through PPI. DMA double buffering and list feature will also help offload the CPU. I would recommend you to take a look at the Advanced usage section of the SPIM driver if you haven't done it already. Also, the PS for a more low-level description of the peripheral: SPIM — Serial peripheral interface master with EasyDMA

RE: Peripheral interrupt setting with S112

yf13 — Mon, 30 Dec 2019 00:50:26 GMT

My app collects data samples at 16000hz, my IRQ will be triggered when the DMA buffer is fully loaded by the last sample. Thus before the next samples come in 1/16000sec=60us, my IRQ needs be finished so that the new SPIM xfer can be setup, otherwise the old SPIM xfer may corrupt memory.

So from this regard, the timing requirements for the IRQ seems shall be less than 60us. Will this be possible?

RE: Peripheral interrupt setting with S112

Vidar Berg — Fri, 27 Dec 2019 16:26:26 GMT

Hi,

Do you have a certain timing requirement you need to meet? The Softevice is idle most of the time, so the timing impact is generally very low. You can read more about it in the "Interrupt model and processor availability" section of the Softdevice specification document.

RE: Peripheral interrupt setting with S112

Turbo J — Fri, 27 Dec 2019 10:17:41 GMT

[quote userid="85167" url="~/f/nordic-q-a/55999/peripheral-interrupt-setting-with-s112"]Will the delay be smaller when I set counter IRQ to level 3? [/quote]

Only in the rare cases when the softdevice needs to process radios stuff at the same time. Otherwise the delay will be the same.

You cannot use the lower IRQ priorities - the timing for the RADIO interrupts is pretty tight even on the 64MHz devices. The softdevice will produce errors when it detects delayed interrupts.