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<?xml-stylesheet type="text/xsl" href="https://devzone.nordicsemi.com/cfs-file/__key/system/syndication/rss.xsl" media="screen"?><rss version="2.0" xmlns:dc="http://purl.org/dc/elements/1.1/" xmlns:slash="http://purl.org/rss/1.0/modules/slash/" xmlns:wfw="http://wellformedweb.org/CommentAPI/" xmlns:atom="http://www.w3.org/2005/Atom"><channel><title>QSPI 32bit addressing mode</title><link>https://devzone.nordicsemi.com/f/nordic-q-a/56928/qspi-32bit-addressing-mode</link><description>We are using a flash part that is 64 MB in size. It is S25FS512. We are trying to use 32 bit addressing mode by setting sdk config flags. However this does not seem to work. Has this been tested? Is there something else that needs to be done? 
 There</description><dc:language>en-US</dc:language><generator>Telligent Community 13</generator><lastBuildDate>Wed, 19 Feb 2020 12:58:14 GMT</lastBuildDate><atom:link rel="self" type="application/rss+xml" href="https://devzone.nordicsemi.com/f/nordic-q-a/56928/qspi-32bit-addressing-mode" /><item><title>RE: QSPI 32bit addressing mode</title><link>https://devzone.nordicsemi.com/thread/235193?ContentTypeID=1</link><pubDate>Wed, 19 Feb 2020 12:58:14 GMT</pubDate><guid isPermaLink="false">137ad170-7792-4731-bb38-c0d22fbe4515:d613c4a8-c420-4c2f-abbd-e120a3517d03</guid><dc:creator>&amp;#216;yvind</dc:creator><description>&lt;p&gt;Hello,&amp;nbsp;&lt;br /&gt;&lt;br /&gt;Can you please check the parameters in&amp;nbsp;nrf_serial_flash_params_t found in components\libraries\block_dev\qspi\nrf_serial_flash_params.c.&lt;br /&gt;&lt;br /&gt;&lt;span style="text-decoration:underline;"&gt;&lt;/span&gt;See these previous DevZone tickets: &lt;a href="https://devzone.nordicsemi.com/f/nordic-q-a/53944/usb-mass-storage-class-on-external-qspi-flash/234758#234758"&gt;Ticket 1&lt;/a&gt; and &lt;a href="https://devzone.nordicsemi.com/f/nordic-q-a/57708/external-flash-with-usbd_msc-example"&gt;Ticket 2&lt;/a&gt;&lt;/p&gt;
&lt;p&gt;Kind regards,&lt;br /&gt;Øyvind&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item><item><title>RE: QSPI 32bit addressing mode</title><link>https://devzone.nordicsemi.com/thread/234998?ContentTypeID=1</link><pubDate>Tue, 18 Feb 2020 16:28:36 GMT</pubDate><guid isPermaLink="false">137ad170-7792-4731-bb38-c0d22fbe4515:03e68f4d-1d50-49ec-8478-3e3646d3e793</guid><dc:creator>Sumanth Murali</dc:creator><description>&lt;p&gt;Hello &lt;a href="https://devzone.nordicsemi.com/members/oyvind-schei"&gt;Øyvind&lt;/a&gt;, Thanks for the response. We have tried doing this, but it does not really help. Either flash erase fails, or the address space wraps around at 24 bit max.&amp;nbsp;&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item><item><title>RE: QSPI 32bit addressing mode</title><link>https://devzone.nordicsemi.com/thread/234120?ContentTypeID=1</link><pubDate>Thu, 13 Feb 2020 09:09:13 GMT</pubDate><guid isPermaLink="false">137ad170-7792-4731-bb38-c0d22fbe4515:4e852626-d9d6-4911-87e7-abb8fb204bdb</guid><dc:creator>&amp;#216;yvind</dc:creator><description>&lt;p&gt;&lt;a href="https://devzone.nordicsemi.com/members/smurali"&gt;Sumanth Murali&lt;/a&gt;, I have finally got an answer.&amp;nbsp;&lt;br /&gt;&lt;br /&gt;The SDK configuration for 32-bit addressing modem only changes the addressing mode in our peripheral.&lt;/p&gt;
&lt;p&gt;&amp;quot;&lt;em&gt;The external Flash also needs to be told what mode it is expected to work in. This command can be different for different Flash vendors, hence difficult to include in the driver. To do that for this specific Flash part,&amp;nbsp;you&amp;nbsp;need to issue the 4BAM command (section 9.3.12 of&amp;nbsp;the flash datasheet) using a &lt;a href="https://infocenter.nordicsemi.com/topic/ps_nrf52840/qspi.html#custom_instructions"&gt;custom instruction &lt;/a&gt;(described in the QSPI section of the nRF52840 PS). When both the external Flash and the QSPI peripheral are in 4-byte addressing mode, our peripheral uses the commands from the table on page 72 of the Flash part&amp;#39;s datasheet with a 4-byte address.&lt;/em&gt;&amp;quot;&lt;/p&gt;
&lt;p&gt;Hope this helps! Let me know how it works.&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item><item><title>RE: QSPI 32bit addressing mode</title><link>https://devzone.nordicsemi.com/thread/234002?ContentTypeID=1</link><pubDate>Wed, 12 Feb 2020 13:55:52 GMT</pubDate><guid isPermaLink="false">137ad170-7792-4731-bb38-c0d22fbe4515:34273fc0-b2f8-4f66-8507-b4310c62bce2</guid><dc:creator>&amp;#216;yvind</dc:creator><description>&lt;p&gt;My sincere apologies,&amp;nbsp;&lt;a href="https://devzone.nordicsemi.com/members/smurali"&gt;Sumanth Murali&lt;/a&gt;,&lt;/p&gt;
&lt;p&gt;I have not forgotten you, and am still working on a solution.&amp;nbsp;&lt;br /&gt;&lt;br /&gt;-Øyvind&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item><item><title>RE: QSPI 32bit addressing mode</title><link>https://devzone.nordicsemi.com/thread/233573?ContentTypeID=1</link><pubDate>Mon, 10 Feb 2020 14:54:58 GMT</pubDate><guid isPermaLink="false">137ad170-7792-4731-bb38-c0d22fbe4515:f06c56ef-fd67-4875-900c-d7c6bda02727</guid><dc:creator>Sumanth Murali</dc:creator><description>&lt;p&gt;Any update on this??&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item><item><title>RE: QSPI 32bit addressing mode</title><link>https://devzone.nordicsemi.com/thread/231375?ContentTypeID=1</link><pubDate>Tue, 28 Jan 2020 11:35:42 GMT</pubDate><guid isPermaLink="false">137ad170-7792-4731-bb38-c0d22fbe4515:d2bb84ed-9858-442a-b710-777f18a4d8d1</guid><dc:creator>&amp;#216;yvind</dc:creator><description>&lt;p&gt;Hello,&amp;nbsp;&lt;br /&gt;&lt;br /&gt;No, updates I&amp;#39;m afraid. I have forwarded this to our SDK team to assist with this issue. I will get back to you ASAP.&amp;nbsp;&lt;br /&gt;&lt;br /&gt;Kind regards,&lt;br /&gt;Øyvind&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item><item><title>RE: QSPI 32bit addressing mode</title><link>https://devzone.nordicsemi.com/thread/231225?ContentTypeID=1</link><pubDate>Mon, 27 Jan 2020 15:36:15 GMT</pubDate><guid isPermaLink="false">137ad170-7792-4731-bb38-c0d22fbe4515:f6b6e776-55fa-4e8f-9368-b31d3e05a431</guid><dc:creator>avaldes</dc:creator><description>&lt;p&gt;Any update on this? We are succesfully using 24bit mode but changing the SDK as show below&amp;nbsp;&lt;/p&gt;
&lt;p&gt;#define NRFX_QSPI_CONFIG_ADDRMODE 1&lt;/p&gt;
&lt;p&gt;#define QSPI_CONFIG_ADDRMODE 1&lt;/p&gt;
&lt;p&gt;&lt;/p&gt;
&lt;p&gt;Did not seem to make it work. Is there anything that needs to be done beyond this configuration settings in the SDK for 32bit mode to work?&lt;/p&gt;
&lt;p&gt;&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item><item><title>RE: QSPI 32bit addressing mode</title><link>https://devzone.nordicsemi.com/thread/230699?ContentTypeID=1</link><pubDate>Thu, 23 Jan 2020 15:45:32 GMT</pubDate><guid isPermaLink="false">137ad170-7792-4731-bb38-c0d22fbe4515:8e4b348c-8fe2-4c49-80c6-3848fb1a8124</guid><dc:creator>Sumanth Murali</dc:creator><description>&lt;p&gt;We have been using 24 Bit addressing mode, and this works fine upto 16 MB. Above that we need to use 32 bit addressing. When i enable 32 bit addr mode in sdk_config.h, the erase just fails.&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item><item><title>RE: QSPI 32bit addressing mode</title><link>https://devzone.nordicsemi.com/thread/230693?ContentTypeID=1</link><pubDate>Thu, 23 Jan 2020 09:24:42 GMT</pubDate><guid isPermaLink="false">137ad170-7792-4731-bb38-c0d22fbe4515:78022560-ad6c-47ec-a174-9e8dda84ced2</guid><dc:creator>&amp;#216;yvind</dc:creator><description>&lt;p&gt;Hello,&amp;nbsp;&lt;br /&gt;&lt;br /&gt;Can you please elaborate on what is not working? Are you getting any error messages?&amp;nbsp;&lt;br /&gt;&lt;br /&gt;32bit addressing mode has been tested and working as far as I know with the &lt;span&gt;MX25R6435F&lt;/span&gt;. Are you using the QSPI example as a starting point? Please make sure that the interface reflects your device.&amp;nbsp;&lt;/p&gt;
&lt;p&gt;From the datasheet of your device it states:&lt;br /&gt;&lt;em&gt;The address transfers occur on SCK rising edge, in SDR commands, or on every SCK edge, in DDR commands.&lt;br /&gt;&lt;/em&gt;Have you verified this is the case with your application?&lt;/p&gt;
&lt;p&gt;Thanks!&amp;nbsp;&lt;br /&gt;&lt;br /&gt;Kind regards,&lt;br /&gt;Øyvind&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item></channel></rss>