Camera Interface

RE: Camera Interface

haakonsh — Thu, 06 Feb 2020 12:17:53 GMT

Hmm,
At 27MHz you'll have 128/27 = 4 clock cycles to find the next state of the pins and update the GPIO register. That's not feasible.

You'll probably need a minimum of 20 clock cycles of a fully optimized code to bit-bang such an interface, so that's at least a ~20*27MHz = ~540MHz CPU. And that's given that the internal memory bus and GPIO peripheral are fast enough.

You're probably better off looking for a dedicated interface IC.

RE: Camera Interface

Yossi_Boran — Wed, 05 Feb 2020 12:19:55 GMT

8 I/O

HSYNC

VSYNC

PCLK

RE: Camera Interface

haakonsh — Wed, 05 Feb 2020 10:03:23 GMT

how many I/O lines does this interface use?

RE: Camera Interface

haakonsh — Wed, 05 Feb 2020 10:02:23 GMT

Still 16MHz, but the GPIO peripheral is not synched to the 16MHz clock (GPIOTE is), so the CPU might be able to drive them faster than 16MHz.

A 27MHz parallel interface is a bit tricky for ULP cortex-m platforms.

RE: Camera Interface

Yossi_Boran — Wed, 05 Feb 2020 09:37:29 GMT

What is the peripherals rate on nRF5340?

Thanks

RE: Camera Interface

haakonsh — Wed, 05 Feb 2020 09:07:44 GMT

Our peripherals runs on a 16MHz clock, and our CPU's at 64MHz. So that's not really feasible.

Maybe you can bit-bang it with the 128MHz CPU of the new nRF5340, but it depends on how many I/O lines you need.