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<?xml-stylesheet type="text/xsl" href="https://devzone.nordicsemi.com/cfs-file/__key/system/syndication/rss.xsl" media="screen"?><rss version="2.0" xmlns:dc="http://purl.org/dc/elements/1.1/" xmlns:slash="http://purl.org/rss/1.0/modules/slash/" xmlns:wfw="http://wellformedweb.org/CommentAPI/" xmlns:atom="http://www.w3.org/2005/Atom"><channel><title>Libuarte_async bug(s) - missing data / wrong buffer returned.</title><link>https://devzone.nordicsemi.com/f/nordic-q-a/57431/libuarte_async-bug-s---missing-data-wrong-buffer-returned</link><description>Hi, We&amp;#39;ve been having problems trying to implement a high-speed uart communication between the nRF52832 and an STM32. We switched to using libuarte so we can use DMA even though our communication protocol has variable-sized packets Unfortunately, after</description><dc:language>en-US</dc:language><generator>Telligent Community 13</generator><lastBuildDate>Wed, 12 Feb 2020 13:44:21 GMT</lastBuildDate><atom:link rel="self" type="application/rss+xml" href="https://devzone.nordicsemi.com/f/nordic-q-a/57431/libuarte_async-bug-s---missing-data-wrong-buffer-returned" /><item><title>RE: Libuarte_async bug(s) - missing data / wrong buffer returned.</title><link>https://devzone.nordicsemi.com/thread/233995?ContentTypeID=1</link><pubDate>Wed, 12 Feb 2020 13:44:21 GMT</pubDate><guid isPermaLink="false">137ad170-7792-4731-bb38-c0d22fbe4515:ded844b6-2eed-4e2f-ad12-56e3580308c7</guid><dc:creator>thefool</dc:creator><description>&lt;p&gt;Yes, this is quite possible. While testing, we did see some cases where the data was transferred in smaller blocks:&lt;/p&gt;
&lt;pre class="c-mrkdwn__pre"&gt;Rx 17 -&amp;gt; 955&lt;br /&gt;Rx 13 -&amp;gt; 972&lt;br /&gt;Rx 16 -&amp;gt; 985&lt;br /&gt;Rx 16 -&amp;gt; 1001&lt;br /&gt;Rx 7 -&amp;gt; 1017&lt;br /&gt;Rx 6 -&amp;gt; 0&lt;br /&gt;Rx 20 -&amp;gt; 6&lt;br /&gt;Rx 22 -&amp;gt; 26&lt;br /&gt;Rx 15 -&amp;gt; 48&lt;br /&gt;Rx 21 -&amp;gt; 63&lt;br /&gt;Rx 17 -&amp;gt; 84&lt;br /&gt;Rx 13 -&amp;gt; 101&lt;br /&gt;Rx 14 -&amp;gt; 114&lt;br /&gt;Rx 11 -&amp;gt; 128&lt;br /&gt;Rx 13 -&amp;gt; 139&lt;br /&gt;Rx 13 -&amp;gt; 152&lt;br /&gt;Rx 13 -&amp;gt; 165&lt;br /&gt;Rx 15 -&amp;gt; 178&lt;br /&gt;Rx 25 -&amp;gt; 193&lt;br /&gt;Rx 13 -&amp;gt; 218&lt;br /&gt;Rx 13 -&amp;gt; 231&lt;br /&gt;Rx 12 -&amp;gt; 244&lt;br /&gt;Rx 3 -&amp;gt; 256&lt;br /&gt;Rx 18 -&amp;gt; 259&lt;br /&gt;Rx 17 -&amp;gt; 277&lt;br /&gt;Rx 16 -&amp;gt; 294&lt;br /&gt;Rx 17 -&amp;gt; 310&lt;br /&gt;Rx 15 -&amp;gt; 327&lt;/pre&gt;
&lt;p&gt;Even though one packet that we transmit is 255 bytes.&amp;nbsp;&lt;br /&gt;We are transmitting everything available using DMA on the STM as well, so this case only occurs while our firmware is filling the TX buffer at exactly the same time that DMA is transferring the data. Since we fill the buffer with data we are getting from USB, it is possible that there interrupts are delayed, and there are pauses between those small 3-25 byte chunks of data, and there is a chance they&amp;#39;re more than 100us.&amp;nbsp;&lt;/p&gt;
&lt;p&gt;&lt;/p&gt;
&lt;p&gt;So yes, it&amp;#39;s quite possible that there are almost back to back timeouts of 100us, but I think that libuarte should be able to handle that too, even if both back to back timeout handlers are delayed.&amp;nbsp;&lt;br /&gt;Lets just take the first three chunks, and say there were&amp;nbsp;150us delay in between each pair, and that the timeout handler only started in the middle of the 16 byte chunk.&amp;nbsp;&lt;/p&gt;
&lt;p&gt;I think the counter should just keep counting, so when the handler reads it, it would be at 17+13+8=28 bytes. This is what it should tell us in the callback, we copy that data, and tell it to free it. So it moves the pointer by 28 bytes. Immediately following the second handler is called, and reads the counter which is still at 28 or maybe 29 bytes by now, so it returns 0 or 1 byte, then frees that 1 byte and exits.&amp;nbsp;&lt;/p&gt;
&lt;p&gt;I don&amp;#39;t see a reason why the second interrupt handler should somehow fail...&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item><item><title>RE: Libuarte_async bug(s) - missing data / wrong buffer returned.</title><link>https://devzone.nordicsemi.com/thread/233984?ContentTypeID=1</link><pubDate>Wed, 12 Feb 2020 13:15:37 GMT</pubDate><guid isPermaLink="false">137ad170-7792-4731-bb38-c0d22fbe4515:195b734e-4b22-4f4c-80ee-7e8daf36982d</guid><dc:creator>Kenneth</dc:creator><description>&lt;p&gt;Hi,&lt;/p&gt;
&lt;p&gt;If my assumption should be any way correct, it would require that the incoming data from the&amp;nbsp;&lt;span&gt;STM32 is not back to back, but may actually have sporadic delay&amp;#39;s of tens of us between bytes. If that is the case I think it could be that you will have two timeouts of 100us almost back to back, do you have any indication&amp;nbsp;this may be the case by looking at the data from the&amp;nbsp;STM32?&lt;/span&gt;&lt;/p&gt;
&lt;p&gt;&lt;span&gt;Kenneth&lt;/span&gt;&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item><item><title>RE: Libuarte_async bug(s) - missing data / wrong buffer returned.</title><link>https://devzone.nordicsemi.com/thread/233946?ContentTypeID=1</link><pubDate>Wed, 12 Feb 2020 12:03:15 GMT</pubDate><guid isPermaLink="false">137ad170-7792-4731-bb38-c0d22fbe4515:39f4a57a-afc5-4c44-9627-95c99af17873</guid><dc:creator>thefool</dc:creator><description>[quote userid="2111" url="~/f/nordic-q-a/57431/libuarte_async-bug-s---missing-data-wrong-buffer-returned/233140"]My only input is that I would recommend to increase&amp;nbsp;&lt;span&gt;.timeout_us&amp;nbsp;=&amp;nbsp;&lt;/span&gt;&lt;span&gt;100 to 300 (or possible more for testing). Reasoning is that depending on other interrupts that may be occurring (causing the uart to be pending), you want to make sure that you can always handle the uart interrupt in time before the next may occur.&lt;/span&gt;[/quote]
&lt;p&gt;So, after more testing, this did indeed solve&amp;nbsp;or&amp;nbsp;work around our issue in the main project. We will set it to 1ms to be safe.&lt;br /&gt;&lt;br /&gt;However, we fail to understand exactly why this is causing a problem, and think this should be able to be fixed in your libuarte implementation. I don&amp;#39;t see a reason why a delayed interrupt handler should cause libuarte to give us old data, or why an interrupt would need to be handled before the next could occur. After all, these are not uart interrupts, but timer/counter interrupts,right? None of these should do anything to uart, which should happily continue receiving.&lt;/p&gt;
&lt;p&gt;To be honest, I did not fully understand the implementation of libuarte, as I have not spent enough time with PPI to really konw exactly what you guys are doing there, and there are very few&amp;nbsp;comments, so I can&amp;#39;t see exactly where things are going wrong, but I&amp;#39;m assuming these things should be your design goals:&lt;/p&gt;
&lt;ul&gt;
&lt;li&gt;The counter that counts incoming bytes should not be stopped by the timeout, but only be reset by the buffer full event, or actually it should just reset whenever it reaches 128 (or whatever the buffer size is)&lt;/li&gt;
&lt;li&gt;The timeout interrupt handler should just read the counter, check how much was copied last time, and tell us where and how much is new in the buffer.&lt;/li&gt;
&lt;li&gt;The buffer full interrupt should do exactly the same, except it doesn&amp;#39;t need to read the counter. Also, it should prepare the next buffer to write to.&amp;nbsp;&lt;/li&gt;
&lt;/ul&gt;
&lt;p&gt;My assumption is that things start going wrong if we&amp;#39;re getting several timeout interrupts, as well as&amp;nbsp;a buffer full interrupt&amp;nbsp;before the first one can be handled, and that this causes one of the handlers to read data from the wrong buffer.&lt;/p&gt;
&lt;p&gt;As far as we can see, the data we&amp;#39;re seeing in a case like this is several hundred bytes old, so&amp;nbsp;it seems like the counter is read correctly, but it&amp;#39;s reading from a new a previously used buffer. (if it were using the wrong counter value, and reading from the right&amp;nbsp;buffer, the data would be less than 128 bytes old).&lt;/p&gt;
&lt;p&gt;Basically my question to Nordic is: Does libuarte handle the case correclty when one or more timeout interrupts and buffer full interrupts are delayed by the softdevice, and in the worst case the buffer full interrupt is handled before the timeout interrupt?&lt;/p&gt;
&lt;p&gt;And that last part poses the question: if two interrupts have the same priority, is it guaranteed that they are handled in the same order they occured, or do peripherals in the same priority group have an internal priority (eg timer0 always being handled before timer1)? Does the DMA buffer full have a higher priority than the timeout interrupt?&lt;/p&gt;
&lt;p&gt;&lt;/p&gt;
&lt;p&gt;My worry is that our workaround with setting such a long timeout only makes this case much more seldom, so we&amp;#39;re not seeing it during testing, but that it might still occur at some point after all.&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item><item><title>RE: Libuarte_async bug(s) - missing data / wrong buffer returned.</title><link>https://devzone.nordicsemi.com/thread/233752?ContentTypeID=1</link><pubDate>Tue, 11 Feb 2020 13:10:59 GMT</pubDate><guid isPermaLink="false">137ad170-7792-4731-bb38-c0d22fbe4515:9e648796-1402-4b96-8063-4103187a49a7</guid><dc:creator>Krzysztof Chruscinski</dc:creator><description>&lt;p&gt;Hi,&lt;/p&gt;
&lt;p&gt;&lt;/p&gt;
&lt;p&gt;I&amp;#39;ve tried your example and after tweaking it a bit i see no errors. I&amp;#39;ve made following changes:&lt;/p&gt;
&lt;p&gt;- commented out&amp;nbsp;&amp;nbsp;printf(&amp;quot;\r\nUART started.\r\n&amp;quot;); i didn&amp;#39;t check if it is the case but if retarget goes to uart then it will collide with libuarte driving same uart.&lt;/p&gt;
&lt;p&gt;- moved initialization of libuarte after advertising init and adding 1second delay before start. This is to ensure that both boards are up and running before TX is started. If RX is started when TX is ongoing then there is no possibility to synchronize. RX is started in the middle of a byte and received data is garbled&lt;/p&gt;
&lt;p&gt;- changed initilization of&amp;nbsp;last_received_byte to (TX_SIZE- 1) to ensure that first byte is not received as error.&lt;/p&gt;
&lt;p&gt;Source file attached.&lt;/p&gt;
&lt;p&gt;Krzysztof&lt;/p&gt;
&lt;p&gt;&lt;a href="https://devzone.nordicsemi.com/cfs-file/__key/communityserver-discussions-components-files/4/3364.main.c"&gt;devzone.nordicsemi.com/.../3364.main.c&lt;/a&gt;&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item><item><title>RE: Libuarte_async bug(s) - missing data / wrong buffer returned.</title><link>https://devzone.nordicsemi.com/thread/233680?ContentTypeID=1</link><pubDate>Tue, 11 Feb 2020 10:16:57 GMT</pubDate><guid isPermaLink="false">137ad170-7792-4731-bb38-c0d22fbe4515:ea29f844-a620-4eac-b434-e575951b3dde</guid><dc:creator>Gasper</dc:creator><description>&lt;p&gt;Sure, I can make the trace, although that will not help a thing. The low-level UART errors (framing) make sense, they only appear when the libuarte is being initialized/enabled, so a few of those at the beginning isn&amp;#39;t the problem. The problem is the data itself, for which the errors are reported when the buffer fills out, at which point the data is checked and copied to a queue for ble transmission, and then the libuarte buffer is freed.&lt;/p&gt;
&lt;p&gt;Anyway, here is the trace, together with the test project that generated the trace:&amp;nbsp;&lt;a href="https://devzone.nordicsemi.com/cfs-file/__key/communityserver-discussions-components-files/4/trace.tar.gz"&gt;devzone.nordicsemi.com/.../trace.tar.gz&lt;/a&gt;&lt;/p&gt;
&lt;p&gt;The project is tested on two nrf52840_DK boards, so you could test it as well, might be easier than this back and forth.&lt;/p&gt;
&lt;p&gt;On the other hand, increasing the idle timeout on our main project helped the issue, although I still feel it shouldn&amp;#39;t be an issue in the first place, at least not like that. I would understand missing bytes if callback handling took to long (in the real project we don&amp;#39;t parse the data in the callback handler, we just copy it to our main buffer queue).&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item><item><title>RE: Libuarte_async bug(s) - missing data / wrong buffer returned.</title><link>https://devzone.nordicsemi.com/thread/233647?ContentTypeID=1</link><pubDate>Tue, 11 Feb 2020 08:30:21 GMT</pubDate><guid isPermaLink="false">137ad170-7792-4731-bb38-c0d22fbe4515:d7c8f6fd-2ee7-4e34-abea-55d4ebcf9751</guid><dc:creator>Kenneth</dc:creator><description>[quote user="Gasper"]You can find a logic analyzer trace in the csv file:&amp;nbsp;&lt;a href="https://devzone.nordicsemi.com/cfs-file/__key/communityserver-discussions-components-files/4/8473.rx.tar.gz"&gt;8473.rx.tar.gz&lt;/a&gt;. [/quote]
&lt;p&gt;I do not see any errors in this trace?&lt;/p&gt;
&lt;p&gt;This doesn&amp;#39;t really display what I am looking for. I thought maybe you could make a logic analyzer trace (e.g using &lt;a href="https://www.saleae.com/"&gt;https://www.saleae.com/&lt;/a&gt;) where you did a trace of the UART RX pin and toggled a IO on UART errors, this would make it easier to go to the where the issue occurred and look at the actual timing on a bit level for previous bytes (if you were able to also output on UART TX the expected value and received value, then we could really see on a bit level for the previous UART RX what may have happened). The .csv is not detailed enough for this.&amp;nbsp;&lt;/p&gt;
&lt;p&gt;How frequently does an error occur?&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item><item><title>RE: Libuarte_async bug(s) - missing data / wrong buffer returned.</title><link>https://devzone.nordicsemi.com/thread/233498?ContentTypeID=1</link><pubDate>Mon, 10 Feb 2020 12:13:48 GMT</pubDate><guid isPermaLink="false">137ad170-7792-4731-bb38-c0d22fbe4515:056f4d3c-448f-40e1-91b7-99ebb761c48b</guid><dc:creator>Gasper</dc:creator><description>&lt;p&gt;Enabling hfclk doesn&amp;#39;t change anything.&amp;nbsp;&lt;/p&gt;
&lt;p&gt;You can find a logic analyzer trace in the csv file:&amp;nbsp;&lt;a href="https://devzone.nordicsemi.com/cfs-file/__key/communityserver-discussions-components-files/4/8473.rx.tar.gz"&gt;devzone.nordicsemi.com/.../8473.rx.tar.gz&lt;/a&gt;. I&amp;#39;ve truncated the trace at the beginning to where Rx started - the nrf_libuarte_async_enable call returned in the middle of the first 0x62 byte, which is probably the framing error reported at the beginning. The first full buffer is reported (NRF_LIBUARTE_ASYNC_EVT_RX_DATA) after ~2.826ms at timestamp 2.10230902. The log for this trace is:&lt;/p&gt;
&lt;p&gt;&lt;pre class="ui-code" data-mode="text"&gt;&amp;lt;warning&amp;gt; app: Boot
&amp;lt;warning&amp;gt; app: Test TX started.
&amp;lt;info&amp;gt; app: Debug logging for UART over RTT started.
&amp;lt;error&amp;gt; app: NRF_LIBUARTE_ASYNC_EVT_ERROR errorSrc 4
&amp;lt;info&amp;gt; app: Rx 128@x20004B84
&amp;lt;error&amp;gt; app: RX: expected x65, got x89 instead
&amp;lt;error&amp;gt; app: RX: expected x8A, got x8D instead
&amp;lt;error&amp;gt; app: RX: expected x8E, got x91 instead
&amp;lt;error&amp;gt; app: RX: expected x92, got x95 instead
&amp;lt;error&amp;gt; app: RX: expected x96, got x99 instead
&amp;lt;error&amp;gt; app: RX: expected x9A, got x9D instead
&amp;lt;error&amp;gt; app: RX: expected x03, got xA1 instead
&amp;lt;error&amp;gt; app: RX: expected x07, got xA5 instead
&amp;lt;error&amp;gt; app: RX: expected x0B, got xA9 instead
&amp;lt;error&amp;gt; app: RX: expected x0F, got xAD instead
&amp;lt;error&amp;gt; app: RX: expected x13, got xB1 instead
&amp;lt;error&amp;gt; app: RX: expected x17, got xB5 instead
&amp;lt;error&amp;gt; app: RX: expected x1B, got xB9 instead
&amp;lt;error&amp;gt; app: RX: expected x1F, got xBD instead
&amp;lt;error&amp;gt; app: RX: expected x23, got xC1 instead
&amp;lt;error&amp;gt; app: RX: expected x27, got xC5 instead
&amp;lt;error&amp;gt; app: RX: expected x2B, got xC9 instead
&amp;lt;error&amp;gt; app: RX: expected x2F, got xCD instead
&amp;lt;error&amp;gt; app: RX: expected x33, got xD1 instead
&amp;lt;error&amp;gt; app: RX: expected x37, got xD5 instead
&amp;lt;error&amp;gt; app: RX: expected x3B, got xD9 instead
&amp;lt;error&amp;gt; app: RX: expected x3F, got xDD instead
&amp;lt;error&amp;gt; app: RX: expected x43, got xE1 instead
&amp;lt;error&amp;gt; app: RX: expected x47, got xE5 instead
&amp;lt;error&amp;gt; app: RX: expected x4B, got xE9 instead
&amp;lt;error&amp;gt; app: RX: expected x4F, got xED instead
&amp;lt;error&amp;gt; app: RX: expected x53, got xF1 instead
&amp;lt;error&amp;gt; app: RX: expected x57, got xF5 instead
&amp;lt;error&amp;gt; app: RX: expected x5B, got xF9 instead
&amp;lt;error&amp;gt; app: RX: expected x5F, got xFD instead
&amp;lt;error&amp;gt; app: RX: expected x63, got x81 instead
&amp;lt;error&amp;gt; app: Errors: 31 -&amp;gt; when got 128 @ x20004B84
&amp;lt;info&amp;gt; app: Rx 128@x20004C04
&lt;/pre&gt;&lt;/p&gt;
&lt;p&gt;Tx started roughly 20us after Rx. Spacing between packets is roughly 10us. Baudrate is set in fw to&amp;nbsp;460800. Tx packet size is 155 bytes (increasing from 0x00 to 0x9A), Rx buffer size is 128 and the size mismatch is intentional as in the original project we have variable packet lengths. Since this is a data stream (for our use case as well), we don&amp;#39;t particularly care that packet end isn&amp;#39;t detected in this case, but we do need it (and it works fine) for a different mode of operation in our core project.&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item><item><title>RE: Libuarte_async bug(s) - missing data / wrong buffer returned.</title><link>https://devzone.nordicsemi.com/thread/233449?ContentTypeID=1</link><pubDate>Mon, 10 Feb 2020 08:57:09 GMT</pubDate><guid isPermaLink="false">137ad170-7792-4731-bb38-c0d22fbe4515:6c1d2493-ea09-4ea7-a307-969663c3a40f</guid><dc:creator>Kenneth</dc:creator><description>&lt;p&gt;Can you check if starting the HFCLK may help? E.g.&amp;nbsp;nrf_drv_clock_hfclk_request()/sd_clock_hfclk_request().&lt;/p&gt;
&lt;p&gt;Do you have a logic analyzer trace of the serial incomming data? I just want to check the size of the packets, the delay between packets/bytes and baud rate.&lt;/p&gt;
[quote user="Gasper"]As for the errorSrc 0 thing, I found the error, not sure how I&amp;#39;ve missed it before: in libuarte_async.c in the handler for&amp;nbsp;NRF_LIBUARTE_DRV_EVT_ERROR, you didn&amp;#39;t actually copy the errorSrc.[/quote]
&lt;p&gt;Thanks, I will report it.&lt;/p&gt;
&lt;p&gt;Best regards,&lt;br /&gt;Kenneth&amp;nbsp;&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item><item><title>RE: Libuarte_async bug(s) - missing data / wrong buffer returned.</title><link>https://devzone.nordicsemi.com/thread/233333?ContentTypeID=1</link><pubDate>Fri, 07 Feb 2020 14:58:11 GMT</pubDate><guid isPermaLink="false">137ad170-7792-4731-bb38-c0d22fbe4515:50aa2d1c-86bb-4b55-808d-0498c80e4bf0</guid><dc:creator>Gasper</dc:creator><description>&lt;p&gt;Hi, We&amp;#39;re using the latest SDK (16.0.0), but we first ported to 15.0 because that&amp;#39;s what the project is using. I have also increased timeout_us to 500 for testing, but it didn&amp;#39;t change a thing. We&amp;#39;re still seeing a bunch of wrong incoming data, usually in the first RX event. I have confirmed that the other side is sending a continuous stream of bytes from 0x00 - 0x9A, then it resets and starts with 0x00 again. This doesn&amp;#39;t make sense, since it reports values above 0x9A, which are not being sent over the line at all:&amp;nbsp;&lt;/p&gt;
&lt;p&gt;&lt;pre class="ui-code" data-mode="text"&gt;&amp;lt;warning&amp;gt; app: Boot
&amp;lt;error&amp;gt; app: NRF_LIBUARTE_ASYNC_EVT_ERROR errorSrc 4
&amp;lt;error&amp;gt; app: NRF_LIBUARTE_ASYNC_EVT_ERROR errorSrc 4
&amp;lt;warning&amp;gt; app: Test TX started.
&amp;lt;info&amp;gt; app: Debug logging for UART over RTT started.
&amp;lt;error&amp;gt; app: NRF_LIBUARTE_ASYNC_EVT_ERROR errorSrc 4
&amp;lt;info&amp;gt; app: Rx 128@x20004B84
&amp;lt;error&amp;gt; app: RX: expected x65, got xAB instead
&amp;lt;error&amp;gt; app: RX: expected x11, got xD5 instead
&amp;lt;error&amp;gt; app: RX: expected x3B, got xE5 instead
&amp;lt;error&amp;gt; app: RX: expected x4B, got xF5 instead
&amp;lt;error&amp;gt; app: RX: expected x5B, got x85 instead
&amp;lt;error&amp;gt; app: RX: expected x86, got x89 instead
&amp;lt;error&amp;gt; app: RX: expected x8A, got x8D instead
&amp;lt;error&amp;gt; app: RX: expected x8E, got x91 instead
&amp;lt;error&amp;gt; app: RX: expected x92, got x95 instead
&amp;lt;error&amp;gt; app: RX: expected x96, got x99 instead
&amp;lt;error&amp;gt; app: RX: expected x9A, got x9D instead
&amp;lt;error&amp;gt; app: RX: expected x03, got xA1 instead
&amp;lt;error&amp;gt; app: RX: expected x07, got xA5 instead
&amp;lt;error&amp;gt; app: RX: expected x0B, got xA9 instead
&amp;lt;error&amp;gt; app: RX: expected x0F, got xAD instead
&amp;lt;error&amp;gt; app: RX: expected x13, got xB1 instead
&amp;lt;error&amp;gt; app: RX: expected x17, got xB5 instead
&amp;lt;error&amp;gt; app: RX: expected x1B, got xB9 instead
&amp;lt;error&amp;gt; app: RX: expected x1F, got xBD instead
&amp;lt;error&amp;gt; app: RX: expected x23, got xC1 instead
&amp;lt;error&amp;gt; app: RX: expected x27, got xC5 instead
&amp;lt;error&amp;gt; app: RX: expected x2B, got xC9 instead
&amp;lt;error&amp;gt; app: RX: expected x2F, got xCD instead
&amp;lt;error&amp;gt; app: RX: expected x33, got xD1 instead
&amp;lt;error&amp;gt; app: RX: expected x37, got xD5 instead
&amp;lt;error&amp;gt; app: RX: expected x3B, got xD9 instead
&amp;lt;error&amp;gt; app: RX: expected x3F, got xDD instead
&amp;lt;error&amp;gt; app: RX: expected x43, got xE1 instead
&amp;lt;error&amp;gt; app: RX: expected x47, got xE5 instead
&amp;lt;error&amp;gt; app: RX: expected x4B, got xE9 instead
&amp;lt;error&amp;gt; app: RX: expected x4F, got xED instead
&amp;lt;error&amp;gt; app: RX: expected x53, got xF1 instead
&amp;lt;error&amp;gt; app: RX: expected x57, got xF5 instead
&amp;lt;error&amp;gt; app: RX: expected x5B, got xF9 instead
&amp;lt;error&amp;gt; app: RX: expected x5F, got xFD instead
&amp;lt;error&amp;gt; app: RX: expected x63, got x81 instead
&amp;lt;error&amp;gt; app: Errors: 36 -&amp;gt; when got 128 @ x20004B84
&amp;lt;info&amp;gt; app: Rx 128@x20004C04
&amp;lt;info&amp;gt; app: Rx 128@x20004C84
&lt;/pre&gt;&lt;/p&gt;
&lt;p&gt;&lt;/p&gt;
&lt;p&gt;As for the errorSrc 0 thing, I found the error, not sure how I&amp;#39;ve missed it before: in libuarte_async.c in the handler for&amp;nbsp;NRF_LIBUARTE_DRV_EVT_ERROR, you didn&amp;#39;t actually copy the errorSrc. Basically, the .data portion is missing:&amp;nbsp;&lt;/p&gt;
&lt;p&gt;&lt;pre class="ui-code" data-mode="c_cpp"&gt;        nrf_libuarte_async_evt_t evt = {
            .type = NRF_LIBUARTE_ASYNC_EVT_ERROR,
            .data = {
                .errorsrc = p_evt-&amp;gt;data.errorsrc
            }
        };&lt;/pre&gt;&lt;/p&gt;
&lt;p&gt;Now that I&amp;#39;ve added that I get the errorsrc4 == framing error, which makes sense, since the other side is already sending while this side is initializing, meaning RX line is changing, and so we get framing errors (a few, right after initialization).&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item><item><title>RE: Libuarte_async bug(s) - missing data / wrong buffer returned.</title><link>https://devzone.nordicsemi.com/thread/233223?ContentTypeID=1</link><pubDate>Fri, 07 Feb 2020 10:18:14 GMT</pubDate><guid isPermaLink="false">137ad170-7792-4731-bb38-c0d22fbe4515:d1691c16-c032-4bcc-bd51-c3c4ddffb8c4</guid><dc:creator>thefool</dc:creator><description>&lt;p&gt;I&amp;#39;m working with Gasper on this, and when looking at the libuarte implementation, I can&amp;#39;t help but wonder if the byte counter/timer is really the best way to handle getting the amount of bytes received. DMA HAS to know where it should write the next byte it gets from UART, so I&amp;#39;d assume there must be a way to somehow get that information. Whether&amp;nbsp;it&amp;#39;s a register or a memory location...&lt;/p&gt;
&lt;p&gt;ie when the timeout fires, we fetch that information (eg by subtracting the current buffer start pointer from the current dma pointer, which should give us the number of bytes received).&lt;/p&gt;
&lt;p&gt;would this not be possible and save resources (and potential error sources)?&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item><item><title>RE: Libuarte_async bug(s) - missing data / wrong buffer returned.</title><link>https://devzone.nordicsemi.com/thread/233140?ContentTypeID=1</link><pubDate>Thu, 06 Feb 2020 18:41:15 GMT</pubDate><guid isPermaLink="false">137ad170-7792-4731-bb38-c0d22fbe4515:1a8a2f1d-a906-4f03-bd3e-32498b8dcbb5</guid><dc:creator>Kenneth</dc:creator><description>&lt;p&gt;I am not aware of any issue, but using the latest is in general the recommended.&lt;/p&gt;
&lt;p&gt;My only input is that I would recommend to increase&amp;nbsp;&lt;span&gt;.timeout_us&amp;nbsp;=&amp;nbsp;&lt;/span&gt;&lt;span&gt;100 to 300 (or possible more for testing). Reasoning is that depending on other interrupts that may be occurring (causing the uart to be pending), you want to make sure that you can always handle the uart interrupt in time before the next may occur.&lt;/span&gt;&lt;/p&gt;
&lt;p&gt;&lt;span&gt;&amp;quot;errorSrc 0&amp;quot; was very odd, maybe you can set a breakpoint&amp;nbsp;on the error and double check value. Making sure RXD is always pulled up can be something to check.&lt;/span&gt;&lt;/p&gt;
&lt;p&gt;&lt;span&gt;Best regards,&lt;br /&gt;Kenneth&lt;/span&gt;&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item></channel></rss>