<?xml version="1.0" encoding="UTF-8" ?>
<?xml-stylesheet type="text/xsl" href="https://devzone.nordicsemi.com/cfs-file/__key/system/syndication/rss.xsl" media="screen"?><rss version="2.0" xmlns:dc="http://purl.org/dc/elements/1.1/" xmlns:slash="http://purl.org/rss/1.0/modules/slash/" xmlns:wfw="http://wellformedweb.org/CommentAPI/" xmlns:atom="http://www.w3.org/2005/Atom"><channel><title>mask FPU IXC exception</title><link>https://devzone.nordicsemi.com/f/nordic-q-a/57519/mask-fpu-ixc-exception</link><description>We have an neural network running on a 52832 using the floating point unit. We started encountering FPU exceptions so we enabled the FPU IRQ to identify which specific instructions is causing the error. However we started getting thousands of FPU interrupts</description><dc:language>en-US</dc:language><generator>Telligent Community 13</generator><lastBuildDate>Tue, 01 Dec 2020 14:08:31 GMT</lastBuildDate><atom:link rel="self" type="application/rss+xml" href="https://devzone.nordicsemi.com/f/nordic-q-a/57519/mask-fpu-ixc-exception" /><item><title>RE: mask FPU IXC exception</title><link>https://devzone.nordicsemi.com/thread/282701?ContentTypeID=1</link><pubDate>Tue, 01 Dec 2020 14:08:31 GMT</pubDate><guid isPermaLink="false">137ad170-7792-4731-bb38-c0d22fbe4515:a9b7dd41-0786-47b0-a850-3ab3984070f8</guid><dc:creator>Susheel Nuguru</dc:creator><description>&lt;p&gt;Please take a look at nRF53&amp;nbsp;&lt;a title="https://infocenter.nordicsemi.com/topic/ps_nrf5340/fpu.html?cp=3_0_0_6_11" href="https://infocenter.nordicsemi.com/topic/ps_nrf5340/fpu.html?cp=3_0_0_6_11" rel="noopener noreferrer" target="_blank"&gt;FPU - Floating point unit (FPU) exceptions&lt;/a&gt;. The exceptions can be masked with this new additions of the newer member of the nRF family.&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item><item><title>RE: mask FPU IXC exception</title><link>https://devzone.nordicsemi.com/thread/233351?ContentTypeID=1</link><pubDate>Fri, 07 Feb 2020 16:04:09 GMT</pubDate><guid isPermaLink="false">137ad170-7792-4731-bb38-c0d22fbe4515:21df6938-db4f-4e3c-b10c-67d964ac57d6</guid><dc:creator>Anthony Ambuehl</dc:creator><description>&lt;p&gt;That unfortunately does make the FPU interrupt pretty useless.&amp;nbsp; I&amp;#39;ll leave it disabled during our algorithm processing.&amp;nbsp;&amp;nbsp;&lt;/p&gt;
&lt;p&gt;Is it possible to request additional hardware features for future version of the nrf5* series?&amp;nbsp; A&amp;nbsp;mask would be really helpful or simply disconnecting IXC as other vendors have done.&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item><item><title>RE: mask FPU IXC exception</title><link>https://devzone.nordicsemi.com/thread/233261?ContentTypeID=1</link><pubDate>Fri, 07 Feb 2020 12:21:54 GMT</pubDate><guid isPermaLink="false">137ad170-7792-4731-bb38-c0d22fbe4515:e547394e-5ef1-4b65-a60f-5f0965d7a7f5</guid><dc:creator>Susheel Nuguru</dc:creator><description>&lt;p&gt;Hi Anthony,&lt;/p&gt;
&lt;p&gt;If you are getting an FPU_IRQ then we can be quite certain that if this is due to IXC then it is connected to the interrupt.&lt;/p&gt;
&lt;p&gt;You can confirm that this is the exception flag that is generating the FPU exception if inside the FPU_interrupt there is no other flag set apart from IXC. Unfortunately there does not seem to be any masking of exceptions inside the FPU level. The interrupt can only be masked at NVIC level which will mask other exceptions along with IXC.&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item></channel></rss>