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<?xml-stylesheet type="text/xsl" href="https://devzone.nordicsemi.com/cfs-file/__key/system/syndication/rss.xsl" media="screen"?><rss version="2.0" xmlns:dc="http://purl.org/dc/elements/1.1/" xmlns:slash="http://purl.org/rss/1.0/modules/slash/" xmlns:wfw="http://wellformedweb.org/CommentAPI/" xmlns:atom="http://www.w3.org/2005/Atom"><channel><title>can not control P1 with nrf5340_dk_nrf5340_cpuappns configuration</title><link>https://devzone.nordicsemi.com/f/nordic-q-a/59254/can-not-control-p1-with-nrf5340_dk_nrf5340_cpuappns-configuration</link><description>I can control GPIO P0,but can&amp;#39;t control P1, when I load project with nrf5340_dk_nrf5340_cpuapp ns configuration. 
 If I load project with nrf5340_dk_nrf5340_cpuapp configuration, I can control both P0 and P1. 
 
 Why there is no P1 in nrf5340_dk_nrf5340_cpuappns</description><dc:language>en-US</dc:language><generator>Telligent Community 13</generator><lastBuildDate>Fri, 27 Mar 2020 01:16:00 GMT</lastBuildDate><atom:link rel="self" type="application/rss+xml" href="https://devzone.nordicsemi.com/f/nordic-q-a/59254/can-not-control-p1-with-nrf5340_dk_nrf5340_cpuappns-configuration" /><item><title>RE: can not control P1 with nrf5340_dk_nrf5340_cpuappns configuration</title><link>https://devzone.nordicsemi.com/thread/241984?ContentTypeID=1</link><pubDate>Fri, 27 Mar 2020 01:16:00 GMT</pubDate><guid isPermaLink="false">137ad170-7792-4731-bb38-c0d22fbe4515:ce843e68-4d9e-47d2-8156-f5a10d098673</guid><dc:creator>sean</dc:creator><description>&lt;p&gt;&lt;span&gt;Hi,Simon&lt;/span&gt;&lt;/p&gt;
&lt;p&gt;&lt;span&gt;Thanks to the help of Smile(Nordic FAE), we found the reason why P0.10 P0.25 P0.26 cannot be controlled.&lt;/span&gt;&lt;/p&gt;
&lt;p&gt;&lt;span&gt;In&amp;nbsp;ncs\zephyr\boards\arm\nrf5340_dk_nrf5340\nrf5340_cpunet_reset.c&amp;nbsp;&amp;nbsp;P0.10 P0.12 P0.25 P0.26 use for uart.&lt;/span&gt;&lt;/p&gt;
&lt;p&gt;&lt;span&gt;&lt;img alt=" " src="https://devzone.nordicsemi.com/resized-image/__size/320x240/__key/communityserver-discussions-components-files/4/6505.1.png" /&gt;&lt;/span&gt;&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item><item><title>RE: can not control P1 with nrf5340_dk_nrf5340_cpuappns configuration</title><link>https://devzone.nordicsemi.com/thread/241487?ContentTypeID=1</link><pubDate>Wed, 25 Mar 2020 01:29:14 GMT</pubDate><guid isPermaLink="false">137ad170-7792-4731-bb38-c0d22fbe4515:d6bf1655-0a1c-4dc2-9a48-c74ed8cebc95</guid><dc:creator>sean</dc:creator><description>&lt;p&gt;Hi,Simon&lt;/p&gt;
&lt;p&gt;&lt;span&gt;Thank you for your answer&lt;/span&gt;&lt;/p&gt;
&lt;p&gt;Yes,&lt;span&gt;I later found that there are some pins for special functions.&lt;/span&gt;&lt;/p&gt;
&lt;p&gt;&lt;span&gt;P0.02 P0.03 -&amp;gt;NFC1 NFC2(modify NRF_UICR_S-&amp;gt;NFCPINS, these pins can be configed&amp;nbsp;as gpio)&lt;/span&gt;&lt;/p&gt;
&lt;p&gt;&lt;span&gt;P0.04 -&amp;gt;AIN0 (disable adc in devicetree, this pin can be configed&amp;nbsp;as gpio)&lt;/span&gt;&lt;/p&gt;
&lt;p&gt;&lt;span&gt;P0.19 P0.20 P0.21 P0.22-&amp;gt;Debug uart log output (maintain uart function)&lt;/span&gt;&lt;/p&gt;
&lt;p&gt;P0.13 P0.14 P0.15 P0.16 P0.17 P0.18 -&amp;gt; QSPI,&amp;nbsp;&lt;span&gt;th&lt;/span&gt;&lt;span&gt;e&lt;/span&gt;&lt;span&gt;se pins can be configed&amp;nbsp;&lt;/span&gt;&lt;span&gt;as&lt;/span&gt;&lt;span&gt;&amp;nbsp;gpio&lt;/span&gt;&lt;/p&gt;
&lt;p&gt;&lt;span&gt;P0.08 P0.09 -&amp;gt;I&amp;nbsp;configed these pins as spi port.If disable spi,they can be controled as gpio.&lt;/span&gt;&lt;/p&gt;
&lt;p&gt;&lt;span&gt;&lt;/span&gt;&amp;nbsp;&amp;nbsp;&lt;/p&gt;
&lt;p&gt;&lt;span&gt;But I still don&amp;#39;t know how to control the level flip of the following pins&lt;/span&gt;&lt;/p&gt;
&lt;p&gt;&lt;span&gt;P0.10&amp;nbsp;P0.25 P0.26 (I still don&amp;#39;t know what these pins are configured to do)&lt;/span&gt;&lt;/p&gt;
&lt;p&gt;&lt;span&gt;P0.00 P0.01-&amp;gt;XL1 XL2 (how to config as gpio.I have tried to config to use RC Oscillator in menuconfig but it failed to compile)&lt;/span&gt;&lt;/p&gt;
&lt;p&gt;&lt;span&gt;&lt;img alt=" " src="https://devzone.nordicsemi.com/resized-image/__size/320x240/__key/communityserver-discussions-components-files/4/4705.1.png" /&gt;&lt;/span&gt;&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item><item><title>RE: can not control P1 with nrf5340_dk_nrf5340_cpuappns configuration</title><link>https://devzone.nordicsemi.com/thread/241353?ContentTypeID=1</link><pubDate>Tue, 24 Mar 2020 12:01:23 GMT</pubDate><guid isPermaLink="false">137ad170-7792-4731-bb38-c0d22fbe4515:35f96be6-1feb-4571-a0f8-b1e8a99cde9f</guid><dc:creator>Simon</dc:creator><description>&lt;p&gt;For some pins, a solder bridge needs to be cut in order to use it as normal GPIO. Check out &lt;a href="https://infocenter.nordicsemi.com/index.jsp?topic=%2Fug_nrf5340_pdk%2FUG%2Fnrf5340_PDK%2Fsolder_bridge.html"&gt;nRF53 PDK Solder bridge configutation&lt;/a&gt;&amp;nbsp;for a more detail description.&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item><item><title>RE: can not control P1 with nrf5340_dk_nrf5340_cpuappns configuration</title><link>https://devzone.nordicsemi.com/thread/240749?ContentTypeID=1</link><pubDate>Fri, 20 Mar 2020 06:39:28 GMT</pubDate><guid isPermaLink="false">137ad170-7792-4731-bb38-c0d22fbe4515:858e4871-26cb-4372-a60e-f4ae87b28102</guid><dc:creator>sean</dc:creator><description>&lt;p&gt;Hi&lt;/p&gt;
&lt;p&gt;&lt;span&gt;By modifying the spm.c Kconfig file, I can already control the output of P1.&lt;/span&gt;&lt;/p&gt;
&lt;p&gt;&lt;span&gt;But I still can&amp;#39;t find out why I can&amp;#39;t control part port of P0( only&amp;nbsp;P0.07,P0.11,P0.23,P0.24,P0.27,P0.28,P0.29,P0.30,P0.31 can be controled).&lt;/span&gt;&lt;/p&gt;
&lt;p&gt;main.c&lt;/p&gt;
&lt;p&gt;&lt;span&gt;&lt;img alt=" " src="https://devzone.nordicsemi.com/resized-image/__size/320x240/__key/communityserver-discussions-components-files/4/5100.1.png" /&gt;&lt;/span&gt;&lt;/p&gt;
&lt;p&gt;Kconfig&lt;/p&gt;
&lt;p&gt;&lt;span&gt;&lt;img alt=" " src="https://devzone.nordicsemi.com/resized-image/__size/320x240/__key/communityserver-discussions-components-files/4/1200.2.png" /&gt;&lt;/span&gt;&lt;/p&gt;
&lt;p&gt;&lt;span&gt;spm.c&lt;/span&gt;&lt;/p&gt;
&lt;p&gt;&lt;span&gt;&lt;img alt=" " src="https://devzone.nordicsemi.com/resized-image/__size/320x240/__key/communityserver-discussions-components-files/4/5516.3.png" /&gt;&lt;/span&gt;&lt;/p&gt;
&lt;p&gt;&lt;span&gt;&lt;img alt=" " src="https://devzone.nordicsemi.com/resized-image/__size/320x240/__key/communityserver-discussions-components-files/4/7266.4.png" /&gt;&lt;/span&gt;&lt;/p&gt;
&lt;p&gt;&lt;span&gt;Log&lt;/span&gt;&lt;/p&gt;
&lt;p&gt;&lt;span&gt;&lt;img alt=" " src="https://devzone.nordicsemi.com/resized-image/__size/320x240/__key/communityserver-discussions-components-files/4/3060.5.png" /&gt;&lt;/span&gt;&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item><item><title>RE: can not control P1 with nrf5340_dk_nrf5340_cpuappns configuration</title><link>https://devzone.nordicsemi.com/thread/240593?ContentTypeID=1</link><pubDate>Thu, 19 Mar 2020 09:59:47 GMT</pubDate><guid isPermaLink="false">137ad170-7792-4731-bb38-c0d22fbe4515:c6871a60-4452-41bd-b014-e48f5b5d0539</guid><dc:creator>sean</dc:creator><description>&lt;p&gt;I found not all P0 can be controled.Only P0.07,P0.11,P0.23,P0.24,P0.27,P0.28,P0.29,P0.30,P0.31 can be control&amp;nbsp;as GPIO.&lt;/p&gt;
&lt;p&gt;&lt;img alt=" " src="https://devzone.nordicsemi.com/resized-image/__size/320x240/__key/communityserver-discussions-components-files/4/6862.1.png" /&gt;&lt;/p&gt;
&lt;p&gt;&lt;img alt=" " src="https://devzone.nordicsemi.com/resized-image/__size/320x240/__key/communityserver-discussions-components-files/4/5807.2.png" /&gt;&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item></channel></rss>