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<?xml-stylesheet type="text/xsl" href="https://devzone.nordicsemi.com/cfs-file/__key/system/syndication/rss.xsl" media="screen"?><rss version="2.0" xmlns:dc="http://purl.org/dc/elements/1.1/" xmlns:slash="http://purl.org/rss/1.0/modules/slash/" xmlns:wfw="http://wellformedweb.org/CommentAPI/" xmlns:atom="http://www.w3.org/2005/Atom"><channel><title>Clarification about SPIM - SS pin management for nrf9160</title><link>https://devzone.nordicsemi.com/f/nordic-q-a/60531/clarification-about-spim---ss-pin-management-for-nrf9160</link><description>Hello, 
 i&amp;#39;m trying to understand how the management of the SS pin is (or has to be) performed when using nrf9160 as SPI master. 
 In this post H&amp;#229;kon said that: 
 &amp;quot;Most driver implementations has its own property for SS pin, as this is essentially a GPIO</description><dc:language>en-US</dc:language><generator>Telligent Community 13</generator><lastBuildDate>Wed, 11 Nov 2020 01:35:56 GMT</lastBuildDate><atom:link rel="self" type="application/rss+xml" href="https://devzone.nordicsemi.com/f/nordic-q-a/60531/clarification-about-spim---ss-pin-management-for-nrf9160" /><item><title>RE: Clarification about SPIM - SS pin management for nrf9160</title><link>https://devzone.nordicsemi.com/thread/279380?ContentTypeID=1</link><pubDate>Wed, 11 Nov 2020 01:35:56 GMT</pubDate><guid isPermaLink="false">137ad170-7792-4731-bb38-c0d22fbe4515:6a1b1a37-87cb-47d6-92f0-adb3c41c84b3</guid><dc:creator>kgarland789</dc:creator><description>&lt;p&gt;Hi Kenneth,&lt;/p&gt;
&lt;p&gt;What does your prj.conf look for this example? When I try to instantiate a spi_cs_control struct, I get a &amp;quot;storage size of cs_pin isn&amp;#39;t known&amp;quot; error.&lt;/p&gt;
&lt;p&gt;Thanks,&lt;/p&gt;
&lt;p&gt;-Kyle&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item><item><title>RE: Clarification about SPIM - SS pin management for nrf9160</title><link>https://devzone.nordicsemi.com/thread/247585?ContentTypeID=1</link><pubDate>Thu, 30 Apr 2020 13:34:10 GMT</pubDate><guid isPermaLink="false">137ad170-7792-4731-bb38-c0d22fbe4515:a9894759-6922-478a-843d-e5ba3096f82d</guid><dc:creator>frax84</dc:creator><description>&lt;p&gt;So&amp;nbsp;the software&amp;nbsp;actually pulls CS line LOW and HIGH automatically, without direct gpio write. Nice, this&amp;nbsp;allow to write more compact and error-proof code.&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item><item><title>RE: Clarification about SPIM - SS pin management for nrf9160</title><link>https://devzone.nordicsemi.com/thread/247516?ContentTypeID=1</link><pubDate>Thu, 30 Apr 2020 11:14:03 GMT</pubDate><guid isPermaLink="false">137ad170-7792-4731-bb38-c0d22fbe4515:9b685408-495a-4e25-ad3d-2b38a9d0caad</guid><dc:creator>Kenneth</dc:creator><description>&lt;p&gt;I was thinking the CS logic was handled in hardware, but by experimenting with it I can see it&amp;#39;s handled in software by the driver. So it is possible to use the CS logic in the driver, I made an example below.&lt;/p&gt;
&lt;p&gt;Best regards,&lt;br /&gt;Kenneth&lt;/p&gt;
&lt;p&gt;&lt;a href="https://devzone.nordicsemi.com/cfs-file/__key/support-attachments/beef5d1b77644c448dabff31668f3a47-725ad60744f244c28f13d6c4a8badcb2/main.c"&gt;devzone.nordicsemi.com/.../main.c&lt;/a&gt;&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item><item><title>RE: Clarification about SPIM - SS pin management for nrf9160</title><link>https://devzone.nordicsemi.com/thread/247346?ContentTypeID=1</link><pubDate>Wed, 29 Apr 2020 12:47:01 GMT</pubDate><guid isPermaLink="false">137ad170-7792-4731-bb38-c0d22fbe4515:8530fbe2-bd5b-4f8d-8738-f6738e40a516</guid><dc:creator>frax84</dc:creator><description>&lt;p&gt;Hi Kenneth,&lt;/p&gt;
&lt;p&gt;ty for the answer. Did you test what you said? Because, from Zephyr documentation, i read:&lt;/p&gt;
&lt;p&gt;&lt;pre class="ui-code" data-mode="text"&gt;structspi_cs_control
#include &amp;lt;spi.h&amp;gt;
SPI Chip Select control structure.

This can be used to control a CS line via a GPIO line, instead of using the controller inner CS logic.&lt;/pre&gt;&lt;/p&gt;
&lt;p&gt;It says this is an alternative to &amp;quot;controller inner CS logic&amp;quot;. I understood that &amp;quot;controller inner CS logic&amp;quot; is the one that is not supported in this case, while i thought that spi_cs_control structure had some kind of effect. Unfortunately due to COVID i have not my scope to test the behaviour of the CS line with or without using this structure, but maybe you already tested it&lt;/p&gt;
&lt;p&gt;Thanks,&lt;/p&gt;
&lt;p&gt;Frax&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item><item><title>RE: Clarification about SPIM - SS pin management for nrf9160</title><link>https://devzone.nordicsemi.com/thread/247337?ContentTypeID=1</link><pubDate>Wed, 29 Apr 2020 12:31:24 GMT</pubDate><guid isPermaLink="false">137ad170-7792-4731-bb38-c0d22fbe4515:58599269-499e-44fc-ad93-3e3247a88f89</guid><dc:creator>Kenneth</dc:creator><description>[quote user=""]Have the struct elements &amp;quot;operation&amp;quot; (it has cs_active_high option) and &amp;quot;spi_cs_control&amp;quot; have any effect on the behaviour of the ss-pin? [/quote]
&lt;p&gt;No, likely this could be used if the hardware supported it, but it doesn&amp;#39;t.&lt;/p&gt;
&lt;p&gt;So you end up with&amp;nbsp;the&amp;nbsp;spi_dev_write() you show.&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item></channel></rss>