https://devzone.nordicsemi.com/f/nordic-q-a/6060/gpio-pull-down-up-questionsIs the GPIO pull down/up asserted on the &#39;inside&#39; of the input disconnect switch or at the input/output pad? The diagrams would indicated that it is on the &#39;inside&#39; of the disconnect switch. To help mitigate floating inputs, using input disconnecten-USTelligent Community 13Wed, 18 Mar 2015 04:03:46 GMThttps://devzone.nordicsemi.com/thread/21207?ContentTypeID=1Wed, 18 Mar 2015 04:03:46 GMT137ad170-7792-4731-bb38-c0d22fbe4515:c2c88b67-99c2-41b2-9ca9-b82dff57d033mcintoda<p>The diagram doesn&#39;t show if the pull/up down is on the inside (input buffer side) of the input disconnect switch or not. I think what I am observing is that it&#39;s on the pad (PCB) side not the input buffer side.</p><div style="clear:both;"></div>https://devzone.nordicsemi.com/thread/21206?ContentTypeID=1Mon, 16 Mar 2015 14:29:28 GMT137ad170-7792-4731-bb38-c0d22fbe4515:14df7b43-5ac1-4930-898e-4c4e88099cf4Stefan Birnir Sverrisson<p>1-2. I think it should be considered to be as the diagram in figure 15 in the nRF51 Series Reference Manual v3.0 indicates. You anyway only configure a pull when you configure a pin as input. So when you have input you configure pull configuration to avoid pin signal from floating. When you configure a pin as output, your are driving that pin so it will not be floating.</p> <p>For any GPIO anomalies, look at the <a href="https://www.nordicsemi.com/eng/nordic/Products/nRF51822/PAN-nRF51822/24634">PAN documents available on our web site</a>. For anomalies for the most recent nRF51 third revision chip, look at PAN nRF51822 PAN v3.0. For older nRF51 revisions, look at PAN v2.4.</p><div style="clear:both;"></div>