Accessing aQFN73 inner pins for two layers PCB design

RE: Accessing aQFN73 inner pins for two layers PCB design

Mishka — Thu, 30 Apr 2020 12:19:59 GMT

Hi Marjeris,

thank you for the clarification! While bypassing some outer GPIO pins looked relatively fair, I was not sure about routing the trace along the chip perimeter.

The PCB in subject is the Raybeacon wearable development board. I'm trying to keep it full-featured yet affordable, hence the only two layers design. It was reviewed already and now thanks to this ticket it has got hardware reset linked to a button (not a big deal when attached to SWD, but I admit quite handy on the go).

Thanks a lot for the outstanding support, highly appreciate it!

Sincerely yours,
Mishka

RE: Accessing aQFN73 inner pins for two layers PCB design

Marjeris Romero — Thu, 30 Apr 2020 07:49:16 GMT

Hi Mishka,

Sorry for the late reply. About the coin cell placement, you only need to make sure that there is solid ground right under the chip, so between the chip and the coincell, as long as this ground requirement from the reference design is met there is no problem in having a 2 layer design.

And it's OK to route reset that way as well. Alternatively you could route it through a GPIO pin that is not in used.

If you want you can send your schematic and layout file for a review in a private devzone ticket before ordering prototypes.

Best regards,

Marjeris